While each technology separately provides advantages that result in increased chip speeds and decreased power consumption, the combination of the two technologies, strained-silicon-on-insulator (SSOI), should provide the benefits of both strained silicon and SOI while alleviating some of the design complexity inherent in current SOI technologies.

This article summarizes the fabrication pro-cess and demonstration of a new germanium-free SSOI substrate structure that was recently presented at the 2002 International IEEE SOI Conference in Williamsburg, Va. Key steps in the fabrication of the structure are the epitaxial growth of high-quality silicon germanium (SiGe) and strained-silicon films with excellent surface quality, and the exploitation of the differential oxidation rates of Si and SiGe.

The final SSOI structure that was fabricated and analyzed is shown in the accompanying figure. This novel structure comprises a bulk-silicon substrate, a buried silicon dioxide layer and a strained-silicon film directly on top of the buried oxide layer.

In conventional strained-silicon technology, the strain in the silicon layer is induced epitaxially, placing it on top of a SiGe alloy with a larger lattice constant than that of silicon. Although the strained silicon in this structure is initially produced in the same manner, the strain-inducing SiGe template layer is removed from the structure without any concomitant loss of strain. The resulting SiGe-free SSOI structure has advantages over alternative SSOI structures.

The fabrication sequence for this novel SSOI structure includes the traditional steps for fabricating an SOI structure with a method combining hydrogen implant, wafer bond and exfoliation. The first key to fabricating this structure lies in the ability to fabricate an epitaxial strained-silicon film with an atomically smooth surface. Second is the ability to define the thickness of the final strained-silicon film on the buried oxide without a chemical-mechanical-polishing (CMP) step.

The germanium-free strained-silicon-on-insulator substrate withstood a furnace anneal of 1,000C.

The first critical step for the fabrication of this SSOI structure was the low-pressure chemical-vapor deposition of a relaxed Si0.70Ge0.30 layer on a bulk-silicon substrate. A compositionally graded SiGe layer was used to relax the lattice constant of the Si0.70Ge0.30 film and to minimize the threading-dislocation density in the film. Using a compositionally graded layer, however, introduces a crosshatched film surface roughness of about 5 to 10 nanometers.

Surface roughness of that magnitude effectively prohibits the wafer-bonding step crucial to placing the strained silicon on the insulator handle wafer. Thus, an essential CMP step was used to smooth the SiGe surface before the further deposition of a 50-nm strained-silicon film.

After the deposition of the strained-silicon film, hydrogen was implanted to define the cleave plane required to separate the handle wafer from the substrate with the compositionally graded SiGe buffer.

The wafer with the strained-silicon layer was then wafer-bonded to the handle wafer, which was an oxidized silicon substrate. The strained-silicon film and a portion of the SiGe template layer were transferred to the handle wafer with an annealing process.

Film removal crucial

The next novel and crucial step in the process is the removal of the SiGe film above the strained-silicon film. To accomplish this task a low temperature, steam oxidation and a wet chemical strip were used to selectively oxidize and remove the SiGe film. The resulting structure was a strained-silicon film that was created directly on top of a buried silicon dioxide film on a bulk-silicon substrate.

The strain state of the strained-silicon film was analyzed after fabrication and after annealing steps in the range of 900 to 1,100°C, in order to simulate the high thermal budgets of silicon CMOS processing. For example, the SSOI structure withstood a furnace anneal of 1,000°C for three minutes with no apparent loss of strain or mechanical integrity. This proves that this novel substrate technology has the potential to be easily implemented in traditional silicon CMOS fabrication processes.

The performance benefits of this SSOI structure can be estimated to be the additive benefits of today's partially depleted SOI technology and strained-silicon technology (about 35 to 50 percent circuit-speed improvement).

The technique outlined in this article defines the final film thickness across a wafer epitaxially. This is a big step forward in the feasibility of fully depleted or ultrathin-body SOI technology.

Thomas Langdo is project manager at AmberWave Systems, Corp. (Salem, N.H.)