The Spartan 2e family now includes devices with 514-pin and 410-pin packages, representing a 60 percent leap in I/O over earlier family members. These devices will come with 400,000 and 600,000 system gates, respectively.

Furnished with eight I/O banks, the Spartan 2e devices can handle single-ended and differential pair connections used for 19 distinct I/O standards, including those for chip-to-chip, backplane and memory interfaces. The devices can tolerate voltages from 1.5 to 3.3 volts, according to the company.

Sandeep Vij, vice president of marketing at Xilinx (San Jose, Calif.), said designers are relying on FPGAs to act as a hub to connect different I/O standards and therefore have a pressing need for devices with more pins and I/O capabilities.

"Without a doubt we're seeing a big push from customers that want a lot more pins," he said.

As a result, more FPGA customers are taking a hard look at I/O capability versus price — something ASIC makers are already accustomed to, Vij said. By increasing the Spartan family's pin count along with density, Xilinx thinks it can meet the needs of 65 percent of chip designers who now use ASICs.

"Customers have the logic density they need, so the next parameter becomes I/O count," Vij said. "In the ASIC industry the game became dollar per pin. It was only a matter of time before that happened to FPGAs."

Based on orders of 250,000 units or more, the 410-pin Spartan 2e part will sell for $27 and the 514-pin device goes for $45. Xilinx plans to ship these devices in volume starting in January. Software development tools for the new products will be ready next month, Vij said.

Spartan FPGAs are used in a range of consumer applications, including digital video systems, plasma displays, global positioning systems and automotive telematics. Xilinx has sold 40 million Spartan devices since 1998 — more than any other product in its lineup — and derives 15 percent of its revenues from them, Vij said.