The Synapse 3220 is essentially a user-programmable sub-backplane. Users connect peripheral cores to the Synapse 3220 and then connect the subbackplane to Sonics' SiliconBackplane via the OpenCore Protocol. Alternatively, users can engage Sonics to connect the core to a bus.

James Colgan, product-marketing manager for the Synapse 3220, said that Sonics created the IP to overcome traffic problems commonly encountered in bus-based architectures that hinder the communication between major cores and peripheral cores in an SoC design. He called the 3220 a multithreaded nonblocking transaction core that allows multiple major cores to access peripheral cores simultaneously. With the Sonics tool set that comes with the core, users can control which cores access which peripheral cores and set up the design so that several transactions between cores and peripherals can occur simultaneously.

"Everything that is concerned with the interrupt control, sideband signaling, error handling-all that is done within the 3220," said Colgan.

Colgan said use of the 3220 can also reduce the power consumption associated with bus-based architectures.