In a luncheon address at the International Electron Devices Meeting (IEDM) here, Grove said that as chip densities increase to a billion transistors or more, power is "becoming a limiter of integration."

While high-k dielectrics and clever circuit design may help keep the industry on its traditional curve of doubling device densities every two to three years, those solutions are likely to run out of steam by the end of this decade. Then, designers will have to make more-efficient use of transistors, keeping within a certain power budget.

Indeed, the pursuit of scalable new transistors is turning into a cat-herding contest in the hands of the researchers involved. In the attempt to control the short-channel effect and maintain transistor performance, researchers have been producing thinner and thinner channels.

Devouring monster

But with the much thinner channel comes really horrible leakage current, a monster that has already threatened to devour ordinary bulk silicon designs at 130-nanometer design rules.

In an effort to reduce the leakage, one approach is to surround the channel with gates on two or even three sides. Most commonly this is done with a FinFET structure, in which the whole transistor becomes a tall, narrow bar of silicon sticking up into the surrounding field oxide. The area that will be the channel is stripped, coated with a very thin gate dielectric and then covered with gate material — either all the way around, in which case the channel has gates on three sides, or just on the vertical walls, in which case it is a double-gate device. The added gates give better control over off-current.

But that leaves the problem of threshold voltage. Today, the threshold voltage is set by doping the channel region to establish a particular potential level relative to the polysilicon gate material. Unfortunately, in very thin-channel devices, two things go wrong with that approach. It becomes difficult to control the uniformity of the dopants in the thin-channel film — in fact, it can become difficult to fit them in in sufficient quantities. And the dopant atoms themselves interfere with carrier mobility in the channel.

Hence, researchers are looking at alternatives that leave the channel either lightly doped or entirely intrinsic. That means that something has to be done about the work function of the gate material. At the moment there appear to be three schools of thought: First, leave the gate alone and use device geometry to solve the problem, as advocated by Taiwan Semiconductor Manufacturing Co. The second school, currently the majority, suggests using a carefully formulated silicide gate, in which various metals have been alloyed with the silicon. The third school is experimenting with metal gates of various types. Both of the last two factions control the gate work function by manipulating the gate composition.

Gate oxide must go

Finally, there is the problem of gate dielectric material. Here the number of materials being explored is astonishing: The only apparent consensus is that sooner or later conventional gate oxide will have to go. The problem is that with shrinking dimensions, the gate dielectric is becoming so thin that tunneling current is becoming a major factor in overall device current, creating yet another undesirable leakage path. So researchers are looking at materials to use either as barrier layers in combination with the gate dielectric or in place of it to reduce the tunneling current. At the same time, higher-k materials are being sought to improve the gate's control over the channel.

Not only are large numbers of geometries and materials being explored, but they also are being explored in various combinations. And once a research project settles on a particular recipe of transistor type, channel thickness, dielectric material and thickness, and gate material, then the process implications of the combination have to be worked out.

There's a lot of work to be done — much more than might be suggested by the transistor success stories in the IEDM papers presented here last week.