MPU core vendor ARM Ltd. has added the Integrator/ CM922T-XA10 Core Module to its range of RealView hardware and software integration solutions. The module provides a hardware and software development environment for Altera Corp.'s family of Excalibur embedded processors, ARM said. Based on the ARM922T core, Excalibur devices combine ARM's processing performance with the flexibility of Altera's FPGA technology.
ARM said that extending the ARM Integrator family to incorporate Excalibur processors offers ARM Foundry Program members and system-on-chip and ASIC developers a powerful hardware prototyping and software development environment, enabling user integration of software and hardware intellectual property, such as the ARM PrimeCell peripherals and associated drivers. The ARM Integrator environment aims to reduce development time and increase efficiency and reliability in final silicon by allowing early prototyping of an environment very similar to the end system.
The company said the Integrator/CM922T-XA10 Core Module is compatible with the Integrator AP (ASIC Development Platform) and Integrator CP (Compact Platform) boards. The module may also be used in conjunction with interface modules, such as the ARM Integrator IM-PD1.
For more information visit www.arm.com/devtools/integratorCMXA10<.A> and www.altera.com/products/devices/ arm/arm-index.html.
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Azanda Network Devices used Databahn memory core intellectual property from Denali Software Inc. (Palo Alto, Calif.) to create its Scimitar AZ61100 OC-48 traffic manager/ATM segmentation-and-reassembly (SAR) device, the companies said. Azanda configured Denali's on-chip Databahn memory controllers to provide 400-MHz data transfers from DDR-SDRAM memory devices operating at 200 MHz. Azanda's Scimitar chip performs traffic management and ATM SAR functions at full-duplex OC-48 speeds, delivering a total aggregate bandwidth of 5 Gbits/ second. Azanda representatives said the company plans to use the Denali IP in its next-generation Saber product family of traffic managers and ATM SARs.
Denali's Databahn allows designers to customize a memory controller core to meet performance and interface requirements for their ASIC application. Customization is supported through an online infrastructure at Denali's eMemory.com site. A browser-based graphical user interface lets users fit the core to various performance and interface needs, and also enables simulation-based performance validation. To ensure compatibility with all the latest high-speed memory technologies, the configuration process is integrated with Denali's database of memory component specifications, including all the latest DDRII-SDRAM, DDR-SDRAM, fast-cycle RAM, reduced-latency DRAM and double-data-rate/QDR-SRAM devices.
The silicon-proven Databahn IP is library independent and covers solutions from 0.18-micron to 0.08-micron technologies, and DRAM device frequencies from 100 to 400 MHz (200- to 800-MHz data rate).
Visit www.denali.com and www.azanda.com.
