Both are variations of a capacitor-based DRAM cell, which lets the designs offer higher memory density for a given chip area than more-common SRAM technology while providing similar performance. Moreover, the companies say, they can make their respective memory technologies in a standard CMOS logic process, keeping a lid on cost and not degrading transistor performance.

Manufacturing has been particularly troublesome for IC suppliers offering chips with embedded DRAM. Normally the wafers containing chips laced with on-chip DRAM have to be transported between a DRAM fab line and a logic line, where there are wide differences in things like annealing temperatures and materials used.

A DRAM process, for example, needs temperatures above 1,000C to form the capacitor — about two times above the temperature threshold of a typical logic process. Exposing the transistors to these temperatures can wind up degrading the performance of the logic considerably. Chip makers have tried to mitigate this problem by depositing thick layers of oxide over the transistors, but this process is costly and tends to reduce wafer yields, said Hideya Horikawa, senior design-engineering manager at NEC Electronics America (Santa Clara, Calif.).

To reconcile DRAM and logic technologies, NEC has developed a special DRAM capacitor using two layers of metal separated by a low-k dielectric material. The tungsten used to build the capacitor is the same metal that forms vias in a logic process. This obviates the need for polysilicon, which is normally used for DRAM cells, allowing the DRAM cell formation to mesh with a standard CMOS logic process. Moreover, the temperature never goes above 500C, which is 100C below the maximum temperature of NEC's 0.13-micron logic process, Horikawa said.

"We've already confirmed in silicon that the transistor performance doesn't change," he said.

NEC also said the new process takes fewer mask and processing steps to blend DRAM with logic, though it still requires more testing. The embedded DRAM portion of the chip can now operate at the same voltage as the logic and the I/Os, while consuming eight to 12 times less power than SRAM.

As for density, NEC's embedded DRAM process takes five to eight times less area than SRAM. The 3.5-nanosecond access speed, meanwhile, is comparable to the company's six-transistor, 3-ns SRAM, said Hamid Aslam, senior technical-marketing manager at NEC.

NEC has already implemented the embedded DRAM in 0.18-micron designs, and is now offering it as a standard ASIC macro for its 0.13-micron process technology.

Density doubled

Intellectual-property provider Mosys Inc., meanwhile, said it has developed a way to double the amount of memory it can pack into a given piece of silicon compared with its previous embedded RAM technology. Mosys intends to license the technology, dubbed 1T-SRAM-Q, to other chip companies.

The 1T-SRAM-Q technology is a knockoff of Mosys' three-year-old 1T-SRAM architecture, which uses a flattened capacitor to create a memory bit cell that acts like a standard six-transistor SRAM but takes up roughly half the die area. The latest version of the technology is almost four times more dense than standard SRAM, said Mark-Eric Jones, vice president and general manager of intellectual property at Mosys (Sunnyvale, Calif.).

With the new "Q" technology, Mosys has found a way to fold the capacitor by 90 into a trench etched in the silicon, thereby reducing memory cell area. Mosys estimates that for a 0.13-micron process technology, a megabit of 1T-SRAM-Q takes up 1.05 mm² of die area vs. 1.9 mm² for its existing technology. A six-transistor SRAM, meanwhile, takes up 3.73 mm² of die area, according to Mosys.

One more mask

Mosys had to make some changes to the manufacturing process to build the memory cell. There's one additional mask needed, and new etching and implant steps have been added to form a cavity into which two-thirds of the capacitor is folded.

The mask layer should wind up costing about $10,000; and the extra processing steps should bring up the cost of the wafer by 5 percent. But Jones said that these costs are negligible considering the $10 million to $20 million it costs to build a typical system-on-chip.

Mosys is recommending that its customers switch to the Q technology whenever memory takes more than 10 percent of the die area. Licensing fees will be the same for both technologies, Jones said.

Digging trenches for capacitors has been done before, most notably by IBM, Toshiba and Infineon. But these were for pure DRAM cells, which require a much higher capacitance and very deep trenches. Mosys' memory architecture, however, is based on a multibank scheme that uses a small number of short bit lines, so the capacitance is only about 10 percent of a standard DRAM cell, said Jones. The cell capacitance does not change with the Q technology and the cavity is formed using a standard shallow-trench isolation method common to logic processes.

Moreover, the process requires no extra thermal cycles as with most embedded DRAM modules. Embedded DRAM, however, is still 20 to 30 percent smaller than Mosys' newest architecture for an equivalent process technology, Jones said.

Since the length of the wires shrinks when cell size goes down, the 1T-SRAM-Q technology should also confer a 10 percent improvement in speed and power consumption. The company is also making its error correction technology a standard feature, Jones said.

Mosys' 1T-SRAM-Q technology will be ready for sampling in the second quarter and can be ready for mass production by late in the year, the company said. Jones said an undisclosed customer has already designed the embedded memory into a device that will be manufactured on a 90-nm process technology.