The VMEbus will be a part of that transition by way of an extension to VME called VXS-VMEbus Switched Serial. VXS, also known as VITA 41, will extend the capabilities of VME's traditional 6U high by 160-mm-deep Eurocard form factor by offering a standard method of employing high-speed switched serial fabrics in the VME context.

Under the VXS specification, VMEbus daughtercards (now called "payload cards") are connected via a high-speed P0 connector to a hot-swappable switch card. In VXS each daughtercard would have two 4X channels connecting to one of two switch cards, respectively, wired in a dual-star configuration.

The second switch is optional and if present may be used for high-availability standby or active load balancing. Each one of the links in the 4X pair has been simulated and tested by the VITA 41 working group to run at data rates as high as 10 gigabits/second, although the state of the art in serializer/deserializer (serdes) technology is 3.125 Gbits/s (Table 1). Since the next turn of serdes technology seems to be headed for 6 Gbits/s, the VXS form factor should accommodate at least three generations of serdes.

The addition of a fabric while coincidentally retaining the parallel bus will allow VXS to offer a high degree of compatibility with existing VME board products.

While VXS requires a new backplane, the framers of VXS strived to achieve the maximum compatibility with existing VMEbus products. For example, existing VMEbus cards should plug into a VXS payload slot if the card does not have an existing P0 connector or some other obstruction in the P0 area.

Many switched serial fabric technologies are making news in the market today, and it is not clear which ones will survive and to what degree. To insulate VXS from the trials and tribulations of any one fabric, the VITA 41 standard was structured to accommodate many different fabric technologies, although not at the same time.

The VXS base specification (VXS.0) defines the physical, mechanical and power features that enable high-speed switched serial communication within a VXS-compatible system. Each different fabric technology is defined in a document subordinate to the base specification. For example, VXS.1 builds upon the VXS base specification by describing how VXS boards may communicate using the 4X Infiniband protocol, and VXS.2 describes how VXS boards may communicate using the 4X Serial RapidIO protocol. Other link-technology specifications are being added.

VXS also provides a home for myriad proprietary fabric extensions that have grown on VME over the years. Until the recent announcements regarding the improved speed of the VME bus using the 2eSST protocol, underpowered bus performance sometimes drove users to add another interconnect to their VME chassis.

As a result, many users migrating to VXS will be coming from their own "home brew" fabric that they have bolted on to VME in a proprietary manner. One method of implementing those proprietary high-speed fabrics in a VXS context is through the use of field-programmable gate arrays (FPGAs).

The latest generation of FPGAs offers integrated 3.125-Gbit/s transceiver features including dedicated circuitry for 8B/10B encoding/decoding, clock-data recovery and serdes functions.

Those devices also provide other useful elements like phase-locked loops for clock multiplication and division. Since they are implemented in dedicated hardware, those features provide maximum performance while consuming none of the programmable-logic resources of the device. That set of features makes the FPGAs ideal for serving as the serial interface on the payload card to the switch fabric.

FPGAs will play an important part in accelerating the adoption of VXS, enabling developers to bring VXS-based products to market while mitigating risk. First, by implementing the serial link in FPGAs, users of proprietary fabric extensions will continue to be able to support them while the standards debate over the "best" serial protocol continues.

Should the card vendors choose to support a different serial protocol in their product at some time in the future, they could do so by reconfiguring the FPGA. Reconfigurations are generally brief and designed for minimal impact on the system.

For example, the reconfiguration time of the Stratix GX FPGA is less than 100 milliseconds and during that time, the I/O pins are tri-stated. Depending on developers' product development planning, this reconfiguration could also be supported for cards in the field, providing greater value to their customers. In either case, developers can preserve much of their initial hardware investment and avoid the time and expense associated with redesigning the card with fixed-function devices.

Another way in which FPGAs will benefit developers of VXS-based products is by allowing them to customize the back-end communication to the other components on the payload card. With that customization, developers can tune the performance of mission-critical data transactions, increasing bandwidth, improving reliability or otherwise adding value or providing product differentiation in their specific market.

The increased data flow on and off the card provided by the serial link will be accompanied by corresponding high-speed chip-to-chip communication on the card, potentially relying on one or more interface protocols such as System Packet Interface (SPI), Hypertransport or Utopia. FPGAs can be used to bridge between these and any other protocols used on the card with a high degree of integration. Developers will be assisted in that effort with the intellectual property that FPGA vendors now offer and are developing to implement those chip-to-chip protocols.

Today's FPGAs also include features that will ease the complications of high-speed board design that developers of VXS-based cards will face. The increasing data rates required by VXS-based cards will result in shrinking margins for setup and hold times, reducing the available timing budget for factors like skew, noise and jitter.

On boards with imperfect power supplies and reference planes, electrical noise may also be a factor. The method commonly used to reduce those effects-matching the length of clock and data traces during board layout-is labor-intensive and time-consuming, requiring an accurate analog board simulation, and is difficult, especially with today's high-pin-count devices.

While adequate for some designs, that method is insufficient for higher-speed designs that require data rates in the range of 700 Mbits/s and beyond. In those applications, the increased clock frequencies have reduced the data window or "eye" for setup times to the point where it is difficult to maintain reliable operation.

To address that problem, the latest FPGAs offer built-in circuitry that provides dynamic phase alignment. The goal of DPA is to allow devices to actively respond to changes in the operational board skew. Devices equipped with DPA continuously check the incoming data and adjust the phase of the clock to align with it.