Statistics on design respins for power consumption and the cost savings of low-power devices in consumer electronics indicate that power must be given more consideration in every future ASIC design. Power is starting to show up as a reason for design respins, although the number of respins for power is a small fraction of the number for functional errors. The EDA industry has focused on the functional design problem and developed technology to bring designers better and faster simulators and analysis tools for functionality. Formal verification is being deployed to address the rising complexity of functional verification, but little is being done to help designers face the challenges of low-power design.
Several factors are driving the ASIC and EDA industry toward low-power design. As feature sizes shrink from "deep submicron" to "nanometer," the cost of ASIC design increases. These cost increases are due to both the increasing complexity of the design and the mounting expenses related to mask sets and ASIC production. The escalating economics could guide some designs away from ASICs toward lower-cost solutions. One factor that drives a design to ASICs over using ASSPs, standard components and FPGAs may be the target power of a portable device. Another factor driving designs to ASICs is the cost savings achievable in high-volume consumer devices. If the volume savings on a design proves the economics of using ASIC vs. other design approaches, the total cost of the end system needs to be driven as low as possible. Lower cost is achieved with low-power design, since it reduces power and eliminates the need for costly fans, heat sinks and ceramic packages.
Few tools exist for power analysis, particularly at the architecture and register-transfer level, where the largest power savings can be achieved. At the gate level only a meager number of power analysis tools are available.
In addition, 20th century ASIC design techniques are counter to low power. For instance, the technique of everything's being synchronous to one clock domain to enable synthesis and static timing analysis is one of the highest power-consuming methodologies. Most power is saved manually, through clever architectural decisions to split the design into many clock domains, running each part of the circuit only when required or at as low a clock rate as possible. This multiple clock domain approach may cause trouble for EDA tools and design flows developed around a single clock methodology.
As the economics of ASIC design continue to encourage alternative system implementations, ASICs will still be required in high-end applications, high-volume consumer products and low-power systems. Up to now, the EDA and design communities have focused on the high-end market driven by networking equipment without considering power. I believe that focus must change because the economics of low-power design will drive a new segment of the ASIC market.
James M. Lee is President of the Asic Group (Fremont, Calif.), a design services company, and is the author of 'Verilog Quickstart.'
