SAN MATEO, Calif.—Synopsys Inc. Monday (March 3) announced it has added new features to SoCBIST, an add-on to DFT Compiler for the creation and integration of IP cores that are optimized for test reuse.
In the Synopsys flow, engineers will use the DFT Compiler to automatically synthesizes test reuse IP cores and create IEEE P1450.6 CTL test models for them.
Next, they will use the TetraMAX ATPG tool to generate reusable test patterns for these cores with high fault coverage.
Finally, engineers will use Synopsys SoCBIST. The tool reads the CTL models of these cores and automatically integrates the cores into the overall SoC, reusing pre-supplied core test patterns referenced from the SoC-level pattern set.
In this way, DFT Compiler, TetraMAX ATPG and SoCBIST work together to automate test reuse in IP core-based designs within the Synopsys implementation platform. Synopsys also announced that the ARM-Synopsys Reference Methodology now includes Synopsys' SoC test solution for use with ARM IP core-based design flows.
The ARM-Synopsys Reference Methodology provides standards-based core test flows to mutual customers.
SoCBIST, introduced last year, is an add-on option to DFT Compiler. The new functionality is available with the March 2003 production release. Pricing for DFT Compiler SoCBIST begins at $175,000 US list for a one-year technology subscription license (TSL).
