Combining RF circuitry with relatively large digital blocks and their associated clock and ground distributions can create significant noise issues for the RF designers, including substrate noise and ground bounce.

RF designers are typically knowledgeable about the noise effects between the blocks, through hard knocks and, often, multiple failures. Digital designers tend to worry about their own world, focusing on meeting timing, power and area specs. Clearly, there is a disconnect.

The EDA industry is attempting to offer better solutions for functional simulation (RF with analog and digital). This is a great start. But the new design automation tools have not yet solved the problem of mixed-mode parasitic-noise modeling.

There is good reason for this lack of progress. Complexity in design is pushing the edge of CAD enabling. While behavioral design languages (and the next wave of tools enabling them) such as Verilog-AMS and VHDL-AMS are becoming more essential, the need for robust process design kits (PDKs) is now almost as important as the tools themselves-and arguably, more important.

Adding to the problem, accurate modeling of all the RLC parasitics in a wireless system can be very complex (this is where parasitic inductance starts to pinch). First there is the problem of interconnect modeling, which in itself has very different issues for digital and for RF designers-although they all involve extraction and modeling of R, L and C effects. Then there is package modeling and all the effects that come with it, such as EM coupling between spiral inductors and nearby bond wires and bond pads.

Last, and most eye-opening, is the area of substrate coupling. This is still an unresolved topic, even though numerous tools are now offered through EDA companies and universities. Even in relatively simple designs, black magic used in parasitic-aware RF design methodologies is still the best hope today.

This is not to say that the pc board problems in multichip solutions are easy to model. Routing sensitive analog and digital signals through package parasitics and pc board traces also introduces parasitic RLC noise issues. But here, system integrators have the advantage of more space and little interaction between the RF and digital chips. In building single-chip SoCs, distances in centimeters (typically seen between chips on a board) become microns.

When looking for a culprit, it is easy to pick on the EDA folks for poor tools enabling. Alternatively, we could blame the digital designers, for ignoring the issues in the RF world. Or we could, as many do, blame the RF folks for failing to come up with real magic and first-time-right IP.

Better than the blame game, the answer to successful integration is for all of the involved parties, as well as the foundries, to establish a more tightly integrated approach to building the various enabling pieces focused on the different application spaces-from CAD tools, to PDKs, to well-tested and documented IP. And then there's the whole discussion of multichip packages.

Raminderpal Singh is technical manager for IBM's process design kit development (Burlington, VT.).