Munich, Germany - The chasm between EDA and test vendors continues to be a vexing problem, with each side arguing that the other should try harder to close the divide.

Caught between them, intellectual-property providers must work with both EDA tool vendors and test companies to find ways to make designs testable.

All three sides in the ongoing and seemingly intractable dispute sat down earlier this month to air their views. Not surprisingly, the session at the Design Automation and Test in Europe (DATE) conference here ended up more as a United Nations-style show of diplomatic position-taking than as any real forum for the resolution of integration issues.

Yervant Zorian, chairman of DATE's test-partitioning and system-on-chip test committee, brought together EDA's big three vendors-Cadence, Synopsys and Mentor Graphics-and three test companies-Teradyne, LTX and Inovys. Sitting between them, figuratively if not literally, were IP providers LogicVision and Intellitech.

"We were hoping to enlighten the audience about the views of EDA and ATE executives on test," said Zorian, chief scientist at Logic Vision, who co-moderated the forum with EE Times' Nicolas Mokhoff. "With the increasing number of liaisons between Design for Test providers and test equipment companies, an update on their views is very timely." DATE occurs about midway between the International Test Conference last October and June's Design Automation Conference, two venues where test and design are exclusive domains.

Bridging the divide

Cadence Design Systems' Rahul Razdan, corporate vice president for system functional verification, told the panel that to bridge today's divide, tool makers and testers must understand each other's responsibilities. "On the system-design side there is a need to be aware of all the elements that make up what I call manufacturing-aware design, and on the test side, one needs to be aware of all the requirements for design-aware manufacturing."

Razdan also shed some light on Cadence's time line in the test arena. Asked about the integration of IBM's Test Group, which Cadence acquired last October as the International Test Conference was under way, Razdan said that progress was being made and that EDA test solutions will be part of the company's design-to-manufacturing design flow being announced at the Design Automation Conference in June.

Antun Domic, senior vice president and general manager of the Nanometer Analysis and Test business unit at Synopsys, said it was essential to reduce test costs and increase quality. Typically, he said, a chip today is built at 130 nanometers and below, has more than 10 million gates and runs in excess of 300 MHz. Since a chip like that carries a price tag above $10 mil-lion and includes hard-to-test complex mixed analog/digital blocks, "the high-level goal should be an automation and interoperability environment" from design through production, Domic said.

Among EDA's three biggest vendors, Synopsys may have the broadest engagement with ATE vendors. Specifically, Synopsys automates the closed-loop diagnostics flow between an ATE and its TetraMax for automatic test-pattern generation processing using the IEEE 1450 Standard Test Interface Language (STIL). "We are committed to STIL and to the CTL [the proposed common test language of IEEE 1450.6]," said Domic.

"It's a delicate balancing act among business and technology issues, and test costs and test quality," said Robert Hum, vice president and general manager of the Design Verification and Test division at Mentor Graphics. He listed the essential requirements for test tools as high test coverage, support for effective at-speed test, and extendible fault models and defect types. "The idea is to minimize test-tool costs on design and process," Hum said.

The test company representatives all insisted their links to EDA are available and ready to roll, but only if the links are specific to their individual equipment. "I don't believe that an open architecture will resolve the EDA-to-test issue," said Marc Levine, vice president of the Enabling Technology Group at Teradyne. "Innovation is stifled this way. Why should anybody try to develop a 2-nanosecond tester when everybody has settled on a 6-ns open-architecture tester?" Levine reiterated the common ATE-industry mantra: Open architectures should be open for each vendor's equipment to work with all EDA tools. It is not necessary, test vendors insist, that each EDA tool interoperate with each test tool.

Levine advocated developing flexible, low-cost DFT testers that support scan and built-in self-test, mixed-signal instruments and low-speed functional test, and that test specific device parameters. He said Teradyne is working to make such configurable and upgradable DFT testers available. "The semiconductor industry will not be stopped [in its scaling] by large testers," said Levine. "We certainly need a higher level of integration between test and EDA."

Paul Sakamoto, chief executive officer of test startup Inovys, said that in times of grim economic news, risk aversion becomes the motto of the day. "We need less-expensive testers and structural test provides the smallest incremental expense, therefore the smallest risk," said Sakamoto. As such, he contended, risk aversion will boost the move to smaller, less costly structural testers.

Caught between EDA and test, IP providers are finding that embedding test structures into chips is one way to make the devices easier to test. "Embedded tests in chips can reduce the time-to-market substantially," said Vinod K. Agrawal, president, chief executive officer and founder of LogicVision, a provider of infrastructure IP designed to ease IC test. "The six to nine months needed to debug a typical ASIC can be done in a month," he said.

"Silicon debug is a growing burden, and embedded test structures provide the highest coverage of all defects," Agrawal said. Embedded test, which provides a unified database for the entire life cycle of a chip, has already been proved on hundreds of designs, he said. "A design with embedded test is validated against an embedded test database and a pass/fail report is issued along with a detailed diagnosis report."

Panelist Christopher J. Clark, president and CEO of Intellitech, agreed that investment in infrastructure IP (IIP) will give returns on the investment put into embedded test development. Intellitech provides IIP to board and system vendors with scan-based tools. "Among the three phases-design, silicon debug and system integration-the EDA industry is focused on a shrinking design phase," said Clark. "Using IEEE 1149.1, internal scan and infrastructure IP can reduce the second phase, and using on-chip and off-chip IP can reduce the third phase."

Clark said investments in IIP in the design phase will provide a better basis for test to be part of the design cycle. With that, EDA vendors could eventually find cost-effective ways to interface with ATE companies, he said.

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