Several companies are looking into MRAM's potential, including Cypress Semiconductor, IBM, Infineon Technologies, Motorola and NEC. All of them see it as a universal replacement for SRAM, DRAM and flash devices. Yet as promising as MRAM seems, it still lags behind FeRAM. In just the past several weeks, three high-profile companies-Hynix, Texas Instruments and Oki-have announced advances on FeRAM products, which target such markets as cell phones, PDAs and smart cards.

The basic attractions of MRAM are its speed and nonvolatility. MRAM can reach theoretical write times down to 2.3 nanoseconds, said IBM Corp. That's more than 1,000 times faster than the fastest nonvolatile flash and is 20 times faster than FeRAM. MRAM access times are as fast as 3 ns, or 20 times faster than DRAM. And since such reads require only 2 milliamps, MRAM consumes less than 1/100 the energy of DRAM, according to IBM research.

The MRAM's resistance to radiation is one of the reasons it is also considered a prime replacement for SRAM, which is expected to suffer more and more from density-induced soft-error rates as it scales below 0.1 micron.

The first hurdle is manufacturability in a high-volume fab. Even extremely slight variations in the oxide, on the order of 0.1 angstrom, can change the magnetic tunneling junction resistance of MRAM by several percentage points, making the device unpredictable. But consistently keeping within the required oxide thickness in a real-world fab environment is tough, especially across an 8-inch wafer. "The most serious problem is the resistance variations but this can be handled with a self-reference sensing scheme," said Gitae Jeong, Samsung's lead researcher on MRAM.

Samsung recently entered the race to commercialize MRAM, a good sign since the company is known for executing well on high-volume, relatively high-margin products. Others have made progress, too. Motorola, which has researched MRAM for several years, is expected to sample a device this year and release a 4-Mbit device for embedded systems sometime in 2004. Toshiba and NEC are working together to develop core technology for a 256-Mbit MRAM by 2004.

On the FeRAM front, Hynix Semiconductor Inc. is sampling 4- and 8-Mbit densities that are manufactured in its 0.25-micron process. Texas Instruments Inc. has already built a 64-Mbit FeRAM module on a 130-nanometer copper logic process, and will introduce embedded FeRAM in its 90-nm process. Japan's Oki Electric Industry Co. has licensed a nondestructive readout FeRAM technology from Symetrix Corp. (Colorado Springs, Colo.). Oki will serve as a foundry for this NDRO FeRAM using its 0.25-micron process, and the companies will collaborate on a 16-Mbit device. It should sample in the fourth quarter.

SST's Sohrab Kianian: focus is on technology in silicon now.

Jim Handy, a Semico analyst covering nonvolatile memory, called 2002 "a coming-of-age for FeRAM, a technology that has hoped to make a mark on the semiconductor memory business for over 18 years."

With all this progress in alternative technologies, one might think the companies sticking to traditional flash would be worried. They are-a little bit. But since these next-generation memories have been talked about for roughly a generation, nobody is losing sleep.

"Our job is to focus on the technology in silicon now and to make it remain competitive even when the hopes and dreams of these universal memory types come true," said Sohrab Kianian, senior director of technology licensing and business development at Silicon Storage Technology Inc.

To that end, SST is getting ready to introduce its self-aligned gate technology in an 0.18-micron process. SST's traditional split-gate flash memory cells require built-in tolerances to align different layers of the memory cell, thereby resulting in a larger flash memory cell size and a higher manufacturing cost. By developing a self-aligned process architecture, SST has eliminated the need for built-in tolerances, leading to a 40 percent reduction in the size of its SuperFlash cell. The company's 130-nm traditional split-gate cell will be ready to go in the second half of next year, and its self-aligned structure will go live in the first half of 2005.

Philips, a major provider of flash for microcontrollers, is also moving ahead with some unique changes, increasing the parallelism in programming and reading per cycle in its latest flash products. "One of the problems as we go down to lower voltages is that the access time isn't going to get faster," said Geoff Lees, director of marketing for Philips Semiconductors' microcontroller business line. "As we get down to 1.2-volt read, this is going to stay resolutely at 50 ns or longer." To compensate, Philips is relying on parallelism. "We have 2 or 4 or 8 bits in a single row, and we can program that via a 128-bit word register," Lees said. "But we read out a full 128-bit word path [and thus] we can get four 32-bit words in a single cycle."

In its self-aligned process architecture SST has eliminated the need for built-in tolerances, leading to a 40 percent reduction in the size of its SuperFlash cell.