The clock is becoming a gating factor in the on-time development of next-generation ICs, contributing to such problems as timing-closure delays, difficulties adopting new process technology and increased power consumption. These and other issues are why clockless-IC design is taking hold in 2003 and will continue to grow until it revolutionizes the way chips are designed.

With perfect clock gating down to the circuit level, asynchronous design is popular today in low-power niches like pagers and smart cards. But recent breakthroughs have boosted asynchronous performance to the point where clockless ICs are a serious performance competitor to clocked logic.

In fact, our experience at Fulcrum is indicative of clockless technology benefits for complex designs. A recent multimillion-transistor IC we fabricated in 150-nanometer technology (generic logic) operates at 450 MHz at nominal voltage. This chip was our first using the 150-nm process and we found that our library was extensible to the new process geometry with no major changes and that the chip was operational on first silicon with no race or glitch errors-despite a 10 percent in-die transistor performance variation.

With perfect clock gating, the average power consumption of this chip is reduced by up to 40 percent over a synchronous alternative. Just as important are other power considerations: a decrease in electromagnetic interference and the ability to voltage scale on the fly for extending battery life in mobile applications.

And, it only gets better as the technology is applied to cutting-edge process technology. We've recently characterized a chip, which we fabricated in the Taiwan Semiconductor Manufacturing Co. 130-nm process, that contains a crossbar switch that delivers 1.2 terabits per second of nonblocking capacity, drawing only a few watts during peak performance.

In the past several decades, the semiconductor industry has excelled at keeping Moore's Law alive with new process advances that have dramatically increased the number of transistors on a chip. Clockless-IC design is perhaps the most efficient way to manage the resulting integration complexity and keep up with Moore's Law in the coming decade.

Mike Zeile is vice president of Marketing at Fulcrum Microsystems (Calabasas Hills, Calif.).