SANTA CRUZ, Calif. — Chip designers are divided when it comes to choosing synchronous or asynchronous resets, according to postings in the latest E-Mail Synopsys Users Group (ESNUG) 409 bulletin. An inquiry from one designer brought in over 20 responses that presented strong arguments for either side.
In the initial inquiry, a designer from Nortel Networks said he was "shocked" when a new group member suggested using synchronous reset flip-flops, given that most ASIC vendors support asynchronous resets, and that Design Compiler will try to build logic in front of a synchronous reset flip-flops. But other designers who posted to ESNUG 409 presented arguments for synchronous resets.
Designs using synchronous resets can synthesize into any cell library, are more glitch-tolerant, and pose fewer design for test problems, wrote one engineer. But he said he preferred asynchronous resets because the design will go into a defined state immediately on the assertion of a reset, without requiring a clock.
Synchronous resets carry extra logic, but must be used if system behavior needs to be controlled as it transitions into the reset state, wrote another designer. Otherwise, he said, synchronous resets are more likely to be "a crutch for those designers that don't want to consider system level issues."
Some spoke of hybrid approaches. "We always use asynchronous reset flops, but with a caveat that we synchronize the release of the reset state," wrote one designer. Another posted RTL Verilog code for an asynchronous reset with a synchronous de-assertion of reset.
One designer said that asynchronous resets add "all the extra complexities and problems of a second clock," pose problems for test, and are intolerant of glitches. But the biggest problem, he said, is that "green" designers are likely to misuse asynchronous resets.
Others advocated asynchronous resets, but provided detailed suggestions for using them correctly and safely. Some noted that the proper reset technique is design dependent, or even ASIC vendor dependent - IBM, for example, discourages asynchronous resets, while other vendors are more tolerant, one engineer noted.
Consultant Cliff Cummings concluded the discussion by reminding readers of a paper he had co-authored on the pros and cons of synchronous and asynchronous resets. The paper is available in the ESNUG download section.
"It's amazing how a simple little reset can be such a methodology topic," Cummings wrote.
