Today, memory "blocks" occupy an increasing portion of system-on-chip (SoC) designs. To achieve maximum density, the memory storage cell often incorporates leading-edge physical design rules that stress the foundry's manufacturing capabilities. As a result, memory blocks are more prone to defects than other types of circuitry such as standard cells and I/Os. To ensure functionality and to increase manufacturing yield, leading-edge memory blocks have to include robust testability and repair solutions. As a result, the increased complexity of verifying the memory block circuit design against the memory block behavioral model becomes critical and demands the use of additional verification techniques.
As a leading provider of quality semiconductor IP to accelerate the design and production of SoC designs, Artisan Components has a long-standing quality assurance (QA) program that incorporates extensive QA and verification procedures for its memory products. The company's memory generator verification procedures include automated parasitic extraction; SPICE-level design margin analysis across hundreds of design and operating corner configurations; physical verification, such as DRC, LVS, and ERC, across all possible generator configurations and circuit design verification, using switch-level, simulation, and equivalency techniques, across all possible generator configurations. Finally, all EDA tool views are generated, extensively tested in each design tool, and are cross-correlated to ensure consistency.
Historically, Artisan's memory generator circuit design verification achieved high levels of QA coverage using switch-level and simulation techniques. With the wide adoption of Artisan's design platform's memory products across several process generations, the control interface for synchronous memory has become widely used. The Artisan memory interface is easily understood from a few simple timing diagrams, so behavioral modeling is not complex. As a result, high quality, vector-based regression tests were developed and could be leveraged from generation to generation to meet the company's stringent validation objectives.
However, as chip designs move to 130- and 90-nanometer process technologies, manufacturing yield concerns are widespread, especially due to the increasing amount of on-chip memory and associated memory storage cell defect densities and device variations. The cost for not incorporating testability and repair solutions for these technologies is becoming prohibitive for chip design companies. Large manufacturers now recommend a repair solution for 130-nanometer chip designs with more than approximately 2-Mbytes of total memory. Artisan has responded to these needs by offering memory IP that includes Flex-Repair' 130-nanometer single-port memory repair solutions and 90-nanometer single- and dual-port memory repair and testability solutions.
With the added complexity of testability and repair solutions, switch-level and simulation verification techniques, alone, cannot adequately achieve sufficient and cost-effective memory block QA coverage. Artisan's memory IP design platforms can incorporate combinations of complex features such as built-in-self-test (BIST), built-in-self-repair (BISR), accelerated retention testing, multiple column redundancy, multiple row redundancy, and soft error repair. Writing vector-based regression tests to achieve sufficient and cost-effective circuit design verification against the behavioral model for all memory block permutations requires a substantial investment in time, which must be weighed against time-to-market needs, and engineering resource, which affects development costs. An accurate and cost-effective solution for memory block verification requires the addition of a verification methodology that is not dependent upon a comprehensive set of test vectors and can natively understand complex and analog circuits, such as sense amplifiers, pre-charged logic, and self-timed loops with a SPICE-like capability.
Combined approach
As a result, Artisan's team decided to employ a solution that combined formal verification coverage within a simulation paradigm. This approach, which is termed sequential equivalence checking, is offered as a verification solution in InnoLogic Systems' ESP-CV product. ESP-CV provides a novel method for verifying custom designs and allows complete verification of the Artisan memories by comparing the SPICE circuit netlist against the behavioral model - all within the simulation paradigm.
Based on symbolic simulation technology, ESP-CV applies variables rather than binary values to the design. These variables propagate across the design and appear as output equations as a function of the variables applied and time elapsed. Since both the SPICE circuit netlist and behavioral model are checked at the same time, both models must produce the same equation. If not, simulation waveforms are dumped to demonstrate the difference.
InnoLogic's CKT (circuit smarts) technology replaces each transistor with an equivalent RC network (using an Elmore delay model) based upon the transistor model properties and calculates signal delay and strength on-the-fly based upon the loading and circuit state. The transistor model properties are derived directly from process SPICE models and can support multiple SPICE model device types. This is especially important when modeling specialty circuits such as memory storage cells and sense amplifiers. CKT eliminates accuracy issues with the traditional method of abstracting the transistor netlist into a gate-level model - an approach deemed insufficient for Artisan's aggressive 90-nanometer designs.
To verify a memory instance, ESP-CV automatically generates a testbench template. In the case of Artisan's memories, a couple of minor modifications were made to the template. The modifications involved setting read-and-write enables, identifying illegal stimulus, and accommodating pipelining by adding cycles of flushing. To ensure adequate coverage, Artisan needed to verify all memory block permutations, not just a single instance. To accomplish this, InnoLogic, in conjunction with Artisan, created a series of scripts that automated the modification of the testbench, thus enabling design engineers and model creators who have no knowledge of ESP-CV to use the tool in a production mode.
Artisan's decision to use InnoLogic's toolset was based on InnoLogic's ability to verify two independently developed models off of the same specification against one another for all instances of generated memories in an automated flow. Innologic's understanding of transistor-level circuit behavior was a key capability. In addition, because ESP-CV operates within a simulation paradigm, it meshes well with existing workflows for both SPICE designers and Verilog model creators. Today, as part of an ongoing process to integrate InnoLogic's toolset into its design flow, Artisan is able to use InnoLogic's toolset to verify its widely-used design platforms that include single- and dual-port memories, single- and two-port register files, and diffusion and via programmable ROMs with little modification.
As today's complex SoCs demand more embedded memories, Artisan will continue to deploy verification solutions that provide customers with the highest quality IP design solutions that enable design-to-silicon success. And, the cornerstone of that process relies on verification techniques that include traditional simulation approaches as well as innovative verification solutions.
