Anaheim, Calif. - The leap to sub-100-nanometer transistor sizes will require open design standards, closer partnerships among EDA companies and new applications that drive volume production, ARM Ltd. chairman Robin Saxby told the Design Automation Conference in a keynote address here last week.
With the IC industry expected to reach 1 billion-transistor ASICs by 2007, Saxby warned that increasing complexity is coming just as designers and chip vendors alike face faster time-to-market pressures. Hence, the EDA industry must come together to map out process rules, improve design verification and validation, and hasten development of new capabilities like deep-ultraviolet technology.
"One hundred nanometers does not mark a discontinuity," Saxby said. "But it does mark the threshold of a severe increase in technical challenges in process and product design." Another challenge, he added, "is how do we bridge the world of system-level design, silicon and software?"
A key consideration in future sub-100-nm designs for mobile products will be power management. "Energy management is critical" and "power reduction is a critical SoC [system-on-chip] design issue," Saxby said. A key reason is that consumers care about features like battery life on cell phones. ARM has been working with partners such as Synopsys Inc. to implement schemes like intelligent energy management and dynamic voltage scaling. An ARM test chip based on the collaboration was taped out in April, Saxby said.
On-chip network
Another design challenge is posed by emerging architectures like "network-on-chip." This scaling of complexity could lead to new capabilities such as high-capacity telecommunications networks, the ARM executive said.
Among the other emerging applications that will drive volume production are automotive and medical electronics, Saxby said. "Auto electronics will be a huge user of all these transistors" for specific applications such as actuators and sensors. One example is navigation systems in cars. The global-positioning system is somewhat unstable in automotive applications. As a result, Saxby said, vehicular systems must include enough hardware to overcome this instability.
Saxby has also promoted medical applications like drug monitoring as an emerging market that will help lead the drive to sub-100-nm devices. Smart cards that store patient information are another example.
With more information moving over wireless networks, security will also be a key consideration for designers of mobile systems, he said.
Given the huge costs of shifting to sub-100-nm transistors, Saxby stressed partnering among EDA companies across multiple disciplines and a growing need to promote design reuse. Too many designers spend too much time designing the same thing, Saxby said.
"Standards and reuse will emerge center stage" as transistor size drops below 100 nm, he added.
Echoing Saxby's call for partnerships, Ted Vucurevich of Cadence Design Systems Inc.'s Office of the Chief Technology Officer told a separate DAC session that rivals will have to work together in some areas "to bring out common solutions for designers" when designs reach 65-nm or finer line widths.
Raul Camposano, senior vice president and chief technology officer of Synopsys, agreed with Vucurevich's assessment. "We need to bring the design information closer to the process sooner and find commonality between EDA tools," Camposano said. "Currently a slew of some 40 different tools are used on the average in a typical design flow. We are starting to develop common APIs [application programming interfaces] to enable the tools to communicate, but we need to pick up the pace."
