Anaheim, Calif. - VeriEZ Solutions Inc., an EDA startup aiming to simplify coding of the OpenVera testbench generation language, introduced its initial product at the Design Automation Conference here last week. The EZVerify verification productivity tool suite will be commercially available in the third quarter, the startup said.
The self-funded VeriEZ (Santa Clara, Calif.), founded last year by Sashi Obilisetty, is in the process of adding field application engineers to support EZVerify. "There are a lot of users and big companies that currently use the OpenVera language," said Obilisetty. "Many of those companies generate pages and pages of code that they would like to ensure is written properly and [would like to] be able to write it more efficiently."
EZVerify has three main components: the EZCheck static linting engine, EZApi custom-rule builder and EZReport verification knowledge extractor. The linter contains 200 rules in its files that can be toggled on or off during linting checks. Users can create their own rules with EZApi. The EZRe-port component scans code and creates a customizable report of problem areas in OpenVera coding.
EZReport is more than a "documentation generator," said Obilisetty, who previously founded DualSoft LLC, a provider of Verilog and VHDL high-level linting tools. DualSoft was purchased in December 2000 by TransEDA plc, and its linter has become TransEDA's VN-Check.
"EZReport is a reuse component," Obilisetty said. "Engineers like to know what is in a component before they make a decision to reuse [it]. This [tool] reads OpenVera modules, creates a document displaying class hierarchy and the thread mechanisms the user has used in OpenVera modules." EZVerify catches errors that would otherwise go undetected in OpenVera code development, she said.
Unassigned functions
"For example, the tool will tell you if a function in OpenVera has not been completely assigned," she said. "This is something that the OpenVera Compiler would not detect. It is a good assumption that a user would want to assign it and so EZCheck would come in, analyze the user's code and point to the unassigned function."
The tool also statically analyzes thread-dependent code and shadow variables. "A lot of users come from a Verilog background and OpenVera is an object-oriented language," said Obilisetty. "The full power of OpenVera only comes out when you use object-oriented capabilities."
She added, "We have a lot of rules that can help you in class design, class analysis and how to communicate between classes. The tool will allow users to develop OpenVera components so they can then be reused in other projects."
The product may seem ill-timed, given the prediction two months ago by Synopsys Inc. CEO Aart de Geus that SystemVerilog would eventually replace OpenVera and VHDL. Obilisetty countered that the transition to SystemVerilog will take some time and that there are still plenty of designers using OpenVera. She also said the tool could evolve to help those now using OpenVera transfer legacy files and make the transition to SystemVerilog.
Obilisetty said VeriEZ may develop a SystemVerilog version of EZVerify as that language evolves but has no plans to develop a similar technology supporting Verisity's "e" language.
Pricing for EZVerify begins at $15,000 for a one-year technology subscription.
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