AMD will bring SOI (silicon-on-insulator) technology to its microprocessors made with 90-nm design rules later this year. For the 65-nm node expected to come to manufacturing in 2005, AMD has a goal of integrating strained silicon channels with SOI substrates, said Ming Ren Lin, department manager of the strategic technology group at AMD in Sunnyvale, Calif.

The next knob to turn would be to integrate metal gates, replacing the doped polysilicon gate electrodes with nickel silicide (NiSi). Lin said the introduction of NiSi metal gates could come before high-k oxides are integrated. That is a new twist on the prevailing idea that in order to implement high-k oxides, which appear to shift the threshold voltage when used with polysilicon gates, the industry may need to bring high-k oxides and metal gates in together.

"I agree 100 percent that high-k needs metal gates. But metal gates may not need high-k. High-k is a huge hurdle, and the industry would be wise to take its time before making that change," Lin said in an interview here.

If the shift to high-k gate oxides are pushed out to 2007, as now appears likely, AMD may introduce NiSi gate electrodes as soon as the 65-nm node as a means of enhancing performance. The metal gates would reduce the problem of polysilicon depletion, which increases the electrical or effective oxide thickness (EOT) at the gate by about 4 Angstroms.

"If we can save four to five Angstroms of EOT by using metal gates, then we may not need to be as aggressive with gate oxide scaling," Lin said.

The shift to metal gates would improve the EOT, and also reduce sheet resistance at the gate, said Qi Xiang, manager of the new materials and process integration section who presented the AMD work at the VLSI symposium Thursday, June 12th.

Xiang estimated that the NiSi gates with strained silicon channels would provide a 20-25 percent performance boost compared with strained silicon and polysilicon gates.

AMD calls its fully silicided approach FUSI. The source and drain region is protected by a silicide layer, and then the polysilicon gate is completely converted to a NiSi metal, all the way down to the gate oxide. The metal composition can be tuned to support the required work function (the energy required to move electrons and holes) for NMOS and PMOS devices, something that is much more difficult to do with deposited metals, Xiang said.

The industry has yet to identify which metals could provide the right work function for CMOS devices, or how to create a process flow for deposited metals, so the FUSI approach may be the only practical approach at the 65- and 45-nm nodes.

It will be interesting to see how the AMD alliance with IBM affects the introduction of FUSI. Though IBM published its own FUSI research work at the 2002 International Electron Devices Meeting, the 65-nm node as currently defined by IBM is too far along in development to include FUSI gates, an IBM manager said.

If it is too late in the 65-nm node definition to include FUSI for IBM, AMD is leaning toward bringing in FUSI then, if possible. The two companies are in discussions now, and David Kyser, director of technology research at AMD, said "we would like to influence IBM's thinking on this topic. We will share ideas on FUSI, and all I can say is that we are very excited about the possibilities with it."

Also at the VLSI symposium, AMD presented 25-nm gate length devices that combined the FUSI gates with fully depleted SOI substrates and 7-nm thick channels. The combination produced what AMD claimed are PMOS devices with the highest reported drive current, of 789 microAmperes per micron at an off current of 27 nanoAmperes per micron at 1.25 V.