Streamlining system-on-chip design is emerging as one of the themes that will dominate this week's Embedded Processor Forum, as several processor companies prepare to describe how their CPU cores can make a difference.

Among those offering an early glimpse of what's on tap are IBM Microelectronics and Tensilica Inc. The two come to the issue from very different points of view: IBM is an ASIC provider with a big stake in chip manufacturing; Tensilica develops malleable processor cores and related tools that it sells to other chip makers.

IBM's approach is to develop what it calls a customized control processor. The idea here is to get the processor and related interconnect and I/Os out of the way of the rest of the chip design. At the same time, it should give software engineers the green light to start their work earlier than usual.

Under this program, the chip designer selects from a catalog of preverified standard processors and decides which peripherals should be left out. IBM then spins out a standard-cell prototype in about 40 days. When the prototype is ready, designers program an FPGA that will contain the custom logic. Once the FPGA has been verified, the software developers can get to work on their code, and IBM can get started on the physical design for the final chip.

"The platform can be given to the software team while the physical design and prototyping are out of the critical path," said Tom Reeves, vice president of custom chip solutions at IBM Microelectronics. "We've taken what used to be a 12-month design time for a 180-nanometer SoC and we are doing it at 130 nm with this technique in six months."

IBM's approach defies those adopted by other ASIC vendors in recent years to shorten the time it takes to create a custom chip. Companies like AMI, Fujitsu, Lightspeed, LSI Logic and NEC have been gravitating toward more generic gate arraylike platforms that are mask programmable. IBM, however, thinks it's important to stick with a standard-cell approach.

Spinning a mask-programmable prototype may take only about 15 days, but at the expense of performance and gate density, IBM believes. "We studied this carefully and decided this solution was best optimized as a standard cell vs. a gate array," Reeves said.

Refining a known design process is also what Tensilica has in mind as it rolls out its latest development tools and language enhancements for its Xtensa processors, which can be configured to run custom instructions. The goal is to help manage the complexity of using multiple processors on a chip. Those designing with Xtensa cores typically use five to eight per chip, said Steve Roddy, director of product marketing at Tensilica.

When a new instruction is entered, for example, the software can now predict how many gates it will require, within a 20 percent margin of error. Previously, a Verilog or VHDL file would have to go through synthesis before this information could be known.

Tensilica said it has come up with a higher-level syntax for its language that lets developers describe a new instruction without defining details like op code or operand encoding. "You can now describe a function without having to articulate all the messy details of what op code slot to use," Roddy said.

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