The integration allows designers to verify and debug chips that incorporate design elements sourced in both VHDL and Verilog, according to the companies.

The simulator now works with Novas Software's Debussy debugging system and Verdi behavior-based debugging system. The integration is enabled by Novas' Design Knowledge Architecture, which stores design information critical to finding errors, and brings in verification knowledge through open application programming interfaces.

Debussy and Verdi extract information from the Verilog and VHDL source code, and then connect that with verification data from the Synopsys VCS MX simulator. The Novas tools use this knowledge to automate tracing of related elements, generate schematic diagrams that isolate any portion of the RTL or netlist and automatically analyze and locate the reasons for problems.