Design reuse is often cited as a useful tool in coping with compressed schedules, smaller design teams and narrowing windows of opportunity. But generally people think of reuse in terms of relatively modest blocks: an embedded processor core here, a peripheral controller there, maybe a bus interface or two. But in a paper at the Hot Chips conference this week at Stanford University, Sun Microsystems Inc. will describe how it took design reuse just about to its extreme-reuse of an entire 64-bit CPU.
The Sun Gemini chip is a dual-processor die carrying twin Ultrasparc-II processors. It is intended for server blades, dense Web servers and other applications where symmetric multiprocessing is the norm and density is a valued asset. The chip clicks along nicely at 1.3 GHz-idling by Pentium standards, but fast for the Sparc world-and consumes a thought-provoking but not unreasonable 30 watts or less in operation at 1.3 volts. It can be operated at as little as 0.9 V for power reduction.
The interesting thing about the Gemini is not so much the architecture-pure Ultrasparc-II-as its design methodology. Rather than launch an entire full-custom CPU design for what is in effect a transitional product, Sun decided to finesse this one. The company picked up the physical design for the Ultrasparc-II, which is at least five years old and was created for a quarter-micron process. Then it did what most foundries will caution you against even trying: a straight linear shrink from 250- to 130-nanometer geometry.
This sounds like a prescription for disaster. Not everything scales linearly when making that huge a process jump, and the whole nature of design rules has changed since the halcyon days of quarter-micron processes. But working closely with longtime foundry partner Texas Instruments Inc., the Sun team developed a set of internal inspection and editing tools that automatically scanned the shrunken design for design-rule violations. This made it possible to automatically insert redundant vias and dummy metal, for example, said Sun senior design director Renu Raman.
That physical design, instantiated twice, formed the heart of the Gemini chip. The core in the new process was quite compact: The 64-bit execution pipe occupies only 8 mm2, for instance, in a 206-mm2 chip. The rest of the area is taken up with new structures: parity circuitry for the Level 1 caches in the CPU cores, 1 Mbyte of L2 cache with error correction, a multiprocessing J-bus and an advanced DDR DRAM controller.
Finally, Sun performed a modern extraction, back-annotated to the design file and reverified the design for timing and signal integrity. That done, the result was a working dual-processor chip.
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