The announcement came at the Boston Synopsys User's Group (BSNUG) conference Monday (Sept. 8).

Synopsys, a strong backer and contributor to SystemVerilog, already has SystemVerilog 3.0 support for Design Compiler and VCS at beta sites. Synopsys' October VCS support for SystemVerilog assertions will also be for beta sites, with production deliveries likely after 6 to 12 weeks, said Swami Venkat, director of product marketing for Synopsys' verification group. Support for other aspects of SystemVerilog 3.1 will come in the first half of 2004, he said.

Venkat noted that VCS already supports OpenVera Assertions (OVA), upon which SystemVerilog 3.1 assertions are based. He added, however, that the Accellera standards organization changed some parts of OVA before bringing it into SystemVerilog 3.1. Moreover, he said OVA support is for pragmas only, whereas the SystemVerilog assertion support will permit in-line assertions.

Venkat said users will be able to write assertions as they describe their design or testbench, without having to turn to an external language. They will also be able to write more efficient protocol checkers and monitors, he said.

Assertions should work with mixed-language designs described in Synopsys' VCS-MX simulator, Venkat added.