However, the electronics industry is very far from reaching that limit with contemporary CMOS, the workhorse circuit regime for digital electronics. Long before it does, there are higher-order limitations in terms of manufacturing possibilities, materials and environmental control that will spark consideration of whether and when it will be beneficial to transition to other technologies during the progression from micro- to nano-electronics.

A more urgent consideration is a second-order limit.

The number of gates per chip has been quadrupling every three years [2], but the gate switching energy has not fallen at the same rate. As a result, the power consumption of the highest-performance chips has been increasing and it has been become harder to remove the heat produced.

The reason for this increasing power consumption is inherent in the switching mechanism of CMOS transistors.

CMOS logic has an advantage over bipolar logic, which consumes power continuously regardless of whether computation is being done or not. But a CMOS gate consumes an energy of CV2/2 each time the output bit changes. Therefore, power consumption increases with clock frequency and the total energy can only be lowered by any-or all-of three methods: reducing the supply voltage, the capacitance or the number of transitions.

And of the three, the voltage probably sets the hardest limit. For silicon with its bandgap of about 1.1-electron-volts, it is not possible to operate transistors much below 1 V. "The key is not the bandgap but the threshold voltage," said Ludo Deferm, vice president of business development at leading manufacturing-process research site center Interuniversities Microelectronics Center (IMEC), in Leuven, Belgium, referring to the voltage applied to the gate of a MOSFET necessary to open a conducting channel between source and drain.

"So it seems likely that way forward is to have specific devices for different applications," said Deferm, indicating that manufacturing processes with dual threshold voltages could become standard. Some transistors would be aimed at performance, such as might be required in the arithmetic logic unit at the heart of a microprocessor, but elsewhere transistors specified for low power consumption would be used.

That argument has apparently been accepted within the industry but is still an exercise in optimization, rather than a head-on push against the limit.

In February 2001, Pat Gelsinger, chief technology officer at Intel Corp., spoke of power consumption and heat as critical issues in semiconductor design in a keynote speech given to the International Solid-State Circuits Conference [3].

Although the wisdom expressed by Gelsinger was well-known even then-particularly in Europe-it was significant that an executive from Intel, which had previously appeared to pursue performance at all costs, was saying it. Gelsinger caught people's attention when he said that, within a decade, microprocessors would run at up to 30 GHz but that, if nothing was done, the power consumption would be 10 kilowatts and the leakage current would be one-third of the power consumption.

"The only way we really know how to reduce active power is to reduce the voltage. We also need to reduce the standby power. But transistors don't work so well at reduced voltage. It's a matter of maintaining performance at low voltage," said Calvin Chenming Hu, chief technology officer of Taiwan Semiconductor Manufacturing Co. Ltd. in a recent interview with Silicon Strategies.

One technique already being used to improve CMOS performance is to fabricate the devices on silicon-on-insulator (SOI) substrates. Although SOI itself does not offer elevated electron or hole mobility, it can produce advantages in terms of reduced capacitances and body leakage currents. There are arguments within the industry about whether the advantages of SOI scale as interconnect capacitance comes to dominate SOI.

Another technique to improve transistor performance is to fabricate the device in a silicon-germanium channel. A relatively small amount of germanium increases electron mobility due to a distortion of the silicon lattice. However, it does require greater concentrations to increase hole mobility, which makes for complications when trying to make complementary MOSFETs for CMOS circuits.

Beyond that are plans to use strained silicon manufactured over a layer of silicon-germanium at 65-nm and 45-nm manufacturing process technology nodes, with the potential to use germanium-over-silicon-germanium at some point further in the future. Germanium has the advantage of an electron mobility more than twice that of silicon and a hole mobility four times higher that of silicon.

However, the adoption of germanium would be a major change in the industry-some would say an untenable disruption-and not without irony, for the material was rejected for integrated circuits 40 years ago because of problems with metal contacts and passivation. Proponents point out that modern manufacturing could now cope with what were then thought of as difficult materials challenges. Indeed, some say that the high-k gate stack that has proved difficult to build on top of silicon could be easier to lay down on germanium.

There again it is argued [4] that raising mobility becomes less important as transistors scale to smaller geometries because of lateral electric fields that cause the carrier velocity to saturate.

Although the active-devices gains possible with materials changes may be needed, they are likely to be only incremental. Thankfully power consumption can be attacked at other levels, the second being that of the transistor.

Also at the transistor level, it is possible to bias the body of the transistor to reduce the leakage current. By controlling the body voltage of a transistor dynamically, Intel believes it is possible to have the best of both worlds: higher speed when the circuit is functioning although with higher leakage power, and lower leakage power when it is not.

And entering into the circuit domain it is possible to add "sleep" and "stacked" transistors. Sleep transistors are "hard-off" devices intended to kill power consumption in neighboring leaky high-performance transistors while they are not in use. Stacked transistors leak less than an individual transistor and, therefore, when a circuit is not speed-critical, two transistors can be employed instead of one. This approach trades area for power consumption, a theme that recurs in the fight against Gelsinger's overheating chips.

As Michel Montier, director of advanced R&D at STMicroelectronics, observed: "For the next two or three generations it will be very difficult, with new materials, new transistor types, and all the optimizations. It will increase the cost of the technology, but it provides the chance to get down to the 15-nm or 10-nm transistor with classical methods."

This has driven research and deployment of copper metal interconnect and low dielectric constant insulator materials but without spectacular success. Problems with the application of low-k materials are thought to have troubled the leading foundries with the introduction of their 130-nm manufacturing process technologies.

The industry is struggling to move the insulator dielectric constant from that of silicon dioxide at about 3.9 down to 2.2. "There's not a lot of room for improvement," said Hans Stork, director of silicon technology development at Texas Instruments. "1.0 is the dielectric constant of vacuum. Conductor-wise, we're really at the limit and at high frequencies inductive effects have to be accounted for globally."

What's more, a gaseous air gap or vacuum gap between conductors is not a good conductor of heat. "There's no order-of-magnitude improvement possible there," said Stork.

"Parallel processing is a good way to trade silicon die area for power consumption. Two blocks doing the same task as one block, at half the clock frequency and at reduced voltage, can save power," TSMC's Hu said. "Also, we can substitute memory for processing power and communications bandwidth, and that can really save power. So you build lots of memory on-chip and use it to cache as much data as possible, and then you don't spend time and energy processing data or fetching it from off-chip."

It has been shown that re-arrangement of software modules to minimize memory calls and changing cache arrangements, their sizes and positions can have orders-of-magnitude effect on power consumption, although at the risk of reducing the general applicability of circuits and making them more application-specific.

Unfortunately, the incremental nature of progress means that the electronics industry is now struggling with electronic design automation tools that primarily trade area for performance. The desire to perform power consumption-driven or power consumption-constrained design has proved difficult to realize.

All of the previous discussion has been based on the assumption of CMOS or a similar logic scheme. And, not surprisingly, the industry has demonstrated that it is reluctant to give up the familiarity of transistor and logic structures that have served it so well.

But, not withstanding the possibility of water cooling-already introduced within some personal computers to avoid noisy fans-power and heat problems are likely to be compelling. One powerful way around the CV2/2 limit of CMOS is to move to adiabatic circuits, also known as charge recovery circuits.

It has been shown theoretically that, if a computation is logically reversible and it is implemented in a physically reversible technology, computing engines could be designed in a such a way that they do not dissipate energy. Of course, such a perfect system, like a perpetual motion machine, is not practically realizable. But several energy-efficient adiabatic logic families have been developed in academia based on MOSFET devices.

Adiabatic Logic Ltd. (Cambridge, England) has developed a design of an output driver for ICs that it claims can save up to 75 percent of the power consumed in inter-chip communications when compared with conventional series terminated drive schemes. In terminated drive schemes, the power is consumed and turned into heat. In Adiabatic's scheme, careful timing of three-pole switching and the use of transistor capacitance allows most of the energy to be re-used during signal transmission from one chip to another.

The adoption of an adiabatic I/O scheme for inter-chip communications could save more than one-third of chip-level power consumption.

Lew Counts, vice president of linear products at Analog Devices Inc., concurs that I/O energy efficiency represents some of the low-hanging fruit, as well as system optimization that includes RF, analog as well as digital. "The progress in digital is wonderful, but that doesn't make the rest irrelevant," he said.

However, it is likely that analog circuits will be less amenable to voltage and critical dimension reduction.

Analog circuit designers recognize the flexibility they have and are resorting to clever techniques for power management. "Burst mode switching regulators, for example, put out power to an output capacitor, where it is stored and then goes to sleep" says Dobkin.

"The frontier of performance will continue to move up," but Counts also said that some analog functions have started to be dis-integrated from digital chips. "We've seen applications go through the integration phase and come out the other side. At 0.13 micron, you may want to have smart partitioning. If your analog functions are compatible with your digital voltages at 1 V and so on, you take the benefit. If not, you have to have a separate chip."

Because of the ability to attack the power and heat problems on many fronts, many experts, Stork included, see no need to go to single-electron-style, carbon nanotube, or electron-spin based devices within the foreseeable future. Intel says that classical silicon or its near derivatives has a least a decade of scaling, if not two, though the chip giant is also discussing the possibility of integrating carbon nanotubes on a silicon platform.

"Single-electron effects tend to be incompatible with speed requirements. It can retain charge but is slow to read and write. You end up with a compromise people don't know how to use. The incremental compatibility with CMOS, with what has gone before is important. It's hard to surpass," said Stork [6].

[1] James D Meindl, Jeffery A Davis "The Fundamental Limit on Binary Switching Energy for Terascale Integration," IEEE Journal of Solid-State Circuits, Vol. 35, No. 10, (October 2000).

[2] Gordon Moore, "Progress in Digital Integrated Electronics," IEDM Tech. Digest, (1975), pages 11-13.

[3] Pat Gelsinger, "Microprocessors for the new millennium: Challenges, opportunities and new frontiers" ISSCC Tech. Digest, pages 22-25 (2001)

[4] Shekhar Borkar "Designing for power-The future of Moore's Law," Part two of three-part interview with Intel Fellow Shekhar Borkar at Intel Labs Web site

[5] X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, et al, "Sub-50nm FinFET: PMOS," IEDM Tech. Digest, (December 1999), pages 67-70.

[6] Kazuo Yano et al. "A 128-Mbit early prototype for gigascale single-electron memories," Digest of Technical Papers. 45th ISSCC 1998, (5-7 Feb. 1998) pages 344-345, 462.

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