To be sure, embedded memory isn't a new concept. Without on-chip SRAM today, most microprocessors wouldn't be able to keep up with instructions coming in at gigahertz speeds. And microcontroller vendors need to demonstrate that they can embed flash memory if they want to make it past the front door of a carmaker. But both memory types have so many shortcomings that chip makers have little choice but to find alternatives.

In some ways, SRAM will be hard to beat. It's the fastest memory available and doesn't require any additional mask steps during manufacturing. Makers of high-speed microprocessors and DSPs have grown so accustomed to these attributes that few, if any, foresee a time processors won't need at least some SRAM for cache memory. "You can't compete with SRAM on speed," said Frank Ramsay, director of strategic marketing for Toshiba America Electronic Components.

One of the biggest drawbacks to SRAM, however, is its large six-transistor cell structure, which means it takes up lots of silicon area. This can be managed so long as the memory is used sparingly. However, today's gigahertz processors require so much memory bandwidth that their cache sizes are now measured in megabytes instead of kilobytes. IBM Microelectronics' latest Power4 processor, for example, is 70 percent SRAM bits.

Subu Iyer, a distinguished engineer at IBM's Microelectronics division, said the chip industry didn't predict such high embedded memory content would appear until 2005. "The appetite for memory is insatiable," he said. "You can make (the processor) very fast, but if the data instructions reside off-chip, it's going to take a long time to get on-chip. The speeds are so fast today that if there's any kind of (cache) miss, there's going to be a huge stall."

As the number of on-chip SRAM bits reaches its limit, so does the leakage current that can be permitted. Iyer estimates that 4.5 Mbytes of SRAM built in the most advanced 90-nm process technology yields a standby current of 100 milliamps, while refresh current is just 2 to 3 percent of this.

Further, SRAM is coming under increased scrutiny because of its vulnerability to soft errors. This is related to the capacitance of the SRAM cell, which falls with each process technology shrink. Less capacitance means there is a higher likelihood that a charged particle, such as alpha particles or cosmic rays, can strike a cell and cause the bit to flip.

Probably the most-talked-about alternative to SRAM is embedded DRAM. Introduced in the mid-1990s, it made an impressive debut in graphics chips for notebook computers and high-end workstations. But the technology stalled as chip vendors struggled to find the right balance between logic performance and memory bit density, while customers balked at the cost of the technology.

The handful of companies that continues to promote embedded DRAM, however, say they've gotten past these earlier shortcomings. In the past, chip companies would develop a logic process and a DRAM process using separate engineering teams and then try to blend the two later. The results were often disappointing: either the logic was too slow or the DRAM was not very dense. That's not the case today. "Embedded DRAM is not an afterthought; it's a fundamental part of the process from day one," Ramsay said.

There's evidence to support renewed interest in embedded DRAM. Sony has tapped Toshiba to build graphics chips with chunks of embedded DRAM for its Playstation 2 game machine. More recently, Analog Devices' latest TigerSharc DSPs come with on-chip DRAM from IBM.

Kevin Leary, product line director at Analog Devices, said his company was able to tweak the embedded DRAM to attain higher speeds by adding a small SRAM cache to every macro for faster page openings and closings. At the same time, it was able to steer clear of problems like the high failure rates that plague SRAM. A network of 100,000 of the DSPs would be more susceptible to soft error failure had they been outfitted with SRAM bits instead of DRAM, he said. "One of those Tigersharcs failing in 100,000 would be catastrophic to the network in terms of availability uptime," he said.

"Things are getting worse for SRAM as much as things are getting better for embedded DRAM," he added.

The most obvious candidate is flash memory, which comes in the form of off-the-shelf memory chips and increasingly as on-chip memory. Many experts, however, say flash memory suffers some inherent disadvantages. For one, it's getting harder to scale with every process technology node. Flash stores bits by charging a floating gate surrounded by silicon dioxide barrier. To get through the barrier, the transistor has to be able to support 4 to 5 V from the source to the drain. But if the channel is too short, there's no stopping the electrons from punching through the gate, which makes in increasingly more difficult to shrink the size of the flash memory cell. "It turns out that the minimum length of the gate between the source and drain is 0.14- to 0.15-microns," said Stefan Lai, vice president of technology at Intel, the leading maker of flash memory chips.

One non-volatile technology that has been proposed as a replacement for flash is ferroelectric RAM. Around since the 80s, FRAM has been championed by many Japanese chip makers, and more recently has gotten attention from companies like Samsung and TI. Performance-wise it is similar to a DRAM, the main difference being that it uses a crystal connected to two electrodes instead of a capacitor.

TI sees FRAM in the way others view embedded DRAM. In a processor-based chip design, a small amount fast SRAM can be used to keep the processor from bogging down, while FRAM will work as a higher level cache. "You bring both the off chip memory and the off chip nonvolatile capabilities on chip," said Ted Moise, FRAM integration manager at TI. "There's a 20 to 30-nanosecond random access and after that it could be in the sub 10 nanoseconds."

Critics of FRAM, however, point out that the cell loses endurance when it reaches a certain number of read cycles and that producers have struggled with FRAM yield since its inception, placing limits on the size of the array. But TI thinks vendors have a much better handle on the materials than in the early days, and that it's now just a matter of tweaking the process. The company expects to field its first embedded FRAM product by 2005.

A relative newcomer to non-volatile memory is magnetic RAM, which has captured the interest of companies like IBM and Motorola. Based on the same principles that govern disk drive read heads, MRAMs store bits by inducing changes in the magneto resistance of materials. In the late 1990s, engineers had found a way to detect changes in resistance as high as 50 percent through a technique known as tunnel junction. This made it easier for the sense amplifiers to detect the signal, and by the late 90s chip vendors were experimenting with small memory arrays made up of cells with one transistor and two layers of magnetic material.

In addition to being non-volatile, MRAMs score high on performance. "It's not as fast as the fastest SRAM but it's comparable to DRAM and it's non volatile," said Bill Gallagher, manager of magnetoelectronics at IBM Research. Gallagher said his company has shown that a 128-kbit array can have an access time of 5 ns and says that a write time of 10-ns is possible. Moreover, it can be three to six times denser than SRAM.

Chalcogenide materials someday will make a better storage mechanism than the floating gate used in flash memory.

One of the big disadvantage of MRAM is that it requires a high current to program, 5 to 10 milliamps, according to Gallagher. But proponents point out that this can be partly mitigated through changes to the architecture, and that the problem isn't as serious as it might seem.

Another non-volatile memory contender that has emerged is phase-change RAM, also known as ovonic or chalcogenide memory. Under investigation at companies such as Intel and Samsung, PRAM uses ceramic material that changes from amorphous resistant to crystalline conductive state when it is heated and cooled, which determines whether the bit is a one or a zero.

There's plenty of skepticism about the use of chalcogenide material as a way to store bits, mostly because it introduces mechanical changes to the material during the heating and quenching cycles. One of these concerns is that the heat could change the properties of neighboring bits.

But Lai said a memory array can be organized so that the bits are staggered to avoid disturbs during programming. As for how the ceramic material will affect the rest of the cell, Lai said Intel has developed a rigid resistive electrode that won't separate from the chalcogenide with time. "That contact is our secret sauce," he said.

It's almost certain that chip makers will need alternatives to today's embedded memory technologies, at least in their current form. The six-transistor cell size of SRAM is getting to be too large and there's mounting evidence that it's becoming more prone to errors. Flash, meanwhile, is getting harder to scale and suffers some inherent endurance problems. The ideal memory would be fast, low-power, error-resistant, durable, non-volatile and cheap to manufacture. Yet no such memory exists today, and it looks as if there are many roads chip makers are going to take, each with its own promises and pitfalls.