Cadence last week announced that it will support "aspects" of SystemVerilog, but not necessarily Accellera's current SystemVerilog 3.1 specification, which Cadence apparently regards as incomplete. That company also announced the appointment of Berman to the newly created position of group director for Cadence's language and standardization strategy.

Separately, Accellera announced that the IEEE has approved ALF, which provides a standard language and semantic representation for design libraries, as IEEE 1603-2003. Additionally, the IEEE approved a new VHDL synthesis subset standard, along with the addition of new features to VHDL.

Meanwhile, Synopsys Inc. (Mountain View, Calif.) is rolling out a third-party SystemVerilog support program that includes more than 30 EDA, consulting, training and intellectual property providers, many of them announcing SystemVerilog support for the first time. Synopsys contributed heavily to SystemVerilog 3.1 and has been its leading backer.

Until now, Cadence has declined to support SystemVerilog, and has instead donated technology to the IEEE 1364 committee, which is starting to develop Verilog 2005. When Accellera missed an August deadline for the donation of SystemVerilog to the IEEE 1364 group, it appeared that two incompatible versions of Verilog might emerge (see Sept. 8, page 1).

Now Cadence is apparently seeking a role as peacemaker. Berman, who chaired the IEEE's Design Automation Standards Committee (DASC) for six years, said he'd do his best to unite Accellera and the IEEE 1364 committee toward a common goal.

"What we're trying to do is make sure that technology developed at Accellera is accepted as an industry and worldwide standard, and that there is a single language," Berman said. "We're going to be very active with both Accellera and the IEEE, and personally, I'm going to try to bridge whatever gaps there are between the organizations."

Berman said Cadence will roll out a detailed plan within the next few weeks for product support for SystemVerilog, but not the current 3.1 specification. "We don't want to commit to the 3.1 spec since it hasn't been released from Accellera, and we don't feel it is a final document at this point," he said. "We feel there's still work to be done."

That stance drew criticism from Rich Goldman, vice president for strategic market development at Synopsys. "SystemVerilog 3.1 was ratified by Accellera May 29," he noted. "There is no debate about whether 3.1 is a standard or a final document." He called on Cadence to commit to supporting all of SystemVerilog 3.1, and to withdraw any Verilog 2005 technology proposals that overlap with it.

Dennis Brophy, Accellera chairman, was less concerned. He noted that EDA vendors are still implementing various features in Verilog 2001. "These things never get supported 100 percent overnight," he said. "We don't find that offensive-these are standard business practices."

While SystemVerilog 3.1 is "released" in the sense of being publicly available, copyright has not been assigned to the IEEE, Brophy noted. Accellera wants to get some implementation experience and prepare a 3.1a "stabilization" release first, he said.

People on all sides of the Verilog standards issue appear to be welcoming Berman. "Victor is very well known in the standards arena, and he understands the mechanism and politics of standards extremely well," Goldman said. "If it's Cadence's intention to create harmony, I think he could be a very good asset."

"Victor helped forge the unity between the VHDL and Verilog camps that resulted in Accellera," Brophy noted. "All of us have a high degree of respect and trust for Victor."

Mike McNamara, chair of the IEEE 1364 working group, said Berman brings "real experience" to the standards area. "He's the guy people look up to in order to figure out how to do things right," McNamara said. "It's like bringing your college professor back."

Berman indicated he may push for some changes, however. "I don't think it makes sense to just say the [IEEE 1364] deadline is over if you don't have stuff in there that users need," he said.

Meanwhile, Synopsys' new SystemVerilog Catalyst Program gives third-party vendors early access to SystemVerilog-based tools, including Synopsys' VCS simulator and HDL Compiler, the front-end language compiler for Design Compiler. VCS already supports SystemVerilog 3.0 and will add SystemVerilog 3.1 assertions this month.

The IEEE 1603 standardization is "a great move forward for nanometer design," said Accellera's Brophy. "The IEEE [standard] makes a solid target that tool suppliers and data creators are going to be able to hit. It sends a signal that ALF is ready for mainstream deployment," he said.

There's already widespread support, said Wolfgang Roethig, chair of Accellera's ALF technical committee and senior engineering manager at NEC Electronics Corp. He said ALF users include EDA vendors Alternative System Concepts Inc., Cadence, Magma, Sequence, Synopsys and Tera Systems Inc.; intellectual property vendors including ARM, Artisan, Library Technologies and Silicon Metrics; and silicon vendors Agere Systems Inc., Intel Corp., Motorola Inc., NEC Corp. and Philips.

Synthesis standards roll

Accellera also announced that the Verilog and VHDL RTL synthesis standards have passed balloting as IEEE 1076.6-1999 and IEEE 1364.1-2002, respectively. Jayaram Bhasker, working group chair for these IEEE standards, noted that the Verilog subset was actually ratified in December, but the VHDL subset was only recently accepted.

In both cases, Bhasker said, the IEEE standards include the Synopsys synthesis subsets but provide additional features that go beyond those subsets, such as the "generate" statement in Verilog 2001.

IEEE 1076-2002 VHDL, meanwhile, has added three enhancements. First, the definition of concatenation and real types is aimed at improving tool portability. Secondly, VHDL now supports multibyte characters within comments, which allows documentation in Asian languages. Finally, buffer mode ports have been improved so they can be easily used with "out" or "inout" mode ports.