Santa Cruz, Calif. - With the SystemVerilog 3.1 language reference manual now available from the Accellera standards organization, more EDA vendors are revealing product plans and expected delivery dates that support the emerging standard. Other companies have indicated that they will support the standard but haven't yet offered details.

Synopsys Inc. appears to have the broadest and earliest implementation. That's not surprising, since the company donated to Accellera much of the technology behind SystemVerilog 3.1. Its VCS Verilog simulator today supports all of SystemVerilog 3.0, and SystemVerilog 3.1 assertion. Full support of 3.1 is promised for the first half of 2004.

Synopsys' Design Compiler synthesis tool supports SystemVerilog 3.0 now, and support for 3.1 is planned for the second half of 2004. The Formality formal equivalence checker will support 3.0 in the first quarter of 2004, and the Vera testbench product will support 3.1 in the first half of 2004.

Cadence Design Systems Inc. recently announced that it will support SystemVerilog, though not the full 3.1 specification (see Oct. 13, page 4). A Mentor Graphics Corp. spokesman said the company will add SystemVerilog support to its ModelSim simulator.

A number of formal verification products are scheduled to offer support for SystemVerilog 3.1 assertions next year. These include 0-In Design Automation's Assertion-Based Verification suite; Jasper De-sign Automation's JasperGold; Real Intent's Verix; TNI-Val-iosys' VN-Check; and Veritable's Verity-Check family.

Some EDA vendors are selective about what they will support. Jasper, for instance, will support a synthesizable subset of SystemVerilog 3.1, a formal subset of assertions. Others are proceeding in a phased way. Aldec, for instance, will add support for 3.1 synthesizable constructs and assertions to its Riviera simulator in the first quarter of 2004 and bring in testbench support in the second quarter.

Novas' Debussy debugger will support SystemVerilog 3.0 by the end of this year, and then bring in 3.1 assertions in the first quarter of 2004. Veritools plans to support SystemVerilog with its Undertow debugger in the second quarter of 2004.

Bringing hardware-assisted verification into the fold, Axis Systems will support SystemVerilog 3.0's synthesizable subset, along with 3.1 assertions, in 2004.

Verific Design Automation, which provides VHDL and Verilog front ends to EDA vendors, is developing a SystemVerilog parser, analyzer and elaborator with support for versions 3.0 and 3.1. This will be available in January, the company said.

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