The announcement comes after two years of regrouping with a back-to-basics mentality within the metro-access arena. The Pleasanton, Calif., company has shelved projects focused on delivering OC-768 (40-Gbit/second) and even OC-192 (10-Gbit/s) rates, in favor of design efforts that can squeeze more bandwidth out of existing architectures or more efficiently use the pipes in place. Both factors have driven the development of such services as virtual concatenation.

Seeing this trend, Deepak Rana, a former executive in Intel Corp.'s Optical Networking Division, formed Crimson in April 2001 to deliver a way for designers to improve integration and reduce cost at the line card level in existing box architectures. With $12.5 million funding, and a team that includes engineers from Cerent, Ciena, Intel and Alcatel in place, Rana is bringing Crimson out of stealth mode and providing details on how it plans to achieve its integration and cost goals.

First off, Crimson has developed what calls a "microcommunication processor." Built around a 250-MHz, 32-bit Tensilica processor core, this CPU architecture handles pointer processing, termination, transcoding, switching and transmux functionality.

At the same time, designers can tap into the configurable Tensilica core to handle control plane processing tasks, a function that is typically relegated to a dedicated processor or dedicated processing card. "Our entire product line fits in existing boxes and provides an exponentially lower cost," Rana said. "At the system level, our technology can lead to a 90 to 95 percent cost reduction."

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The on-board framer is rate-independent and supports OC-3, OC-12 or OC-48 rates, Rana said. The on-board switch is a nonblocking element that supports Sonet, SDH or PDH traffic.

To complement its on-board capabilities, the microcommunication processor architecture comes with a 10-Gbit/s interface on the line side and dual 10-Gbit/s interfaces on the system side-one for active schemes and one for protection. It also has a 2.5-Gbit/s access bus that Rana said can be used for linking up with off-chip FPGAs or dedicated ASICs from companies, such as PMC-Sierra, that perform framing and other tasks.

One of the interesting features of the microcommunication processor lies in the flexibility Crimson provides in tailoring the chip for a particular application. For example, if a designer only wants to tap the chip for cross-connect tasks, Crimson has the ability, at the silicon level, to tailor it for that particular function.

According to Rana, this approach provides manufacturing efficiencies. By supplying the capability to disable certain functions, Rana said Crimson can reuse the same die for different applications, thus allowing the startup to leverage its silicon costs across multiple projects. "We don't need to build five different chips," he said.

Crimson's first chip, called Ruby, is a 0.13-micron device that will start sampling in the first half of 2004 and will include all functions except the termination and transmux capabilities. The company is working on a second-generation 0.13-micron part, called Emerald, that Rana said will include the transmux functionality. Termination capabilities will be added in the third-generation chip, called Sapphire, which will be developed in a 90-nanometer process.

Crimson expects to start shipping its first microcommunication processor in volume in 2005. This chip will be delivered in a 41 x 41-mm, 1,450-ball flip-chip BGA package and will draw 15 watts when configured as a cross-connect and less than 10 W when configured as a framer.

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