San Mateo, Calif. - SiliconPipe, a San Jose, Calif., intellectual-property startup aiming to revolutionize all sorts of interconnect, last week disclosed an application of its technology to memory interfaces that suggests an alternative to the present Jedec road map for the links between core logic and main memory. The approach applies design principles that the company has used to demonstrate serial-backplane connections at up to 40 Gbits/second (see Oct. 13, page 37).

"The present direction in memory interconnect was established in a time of very different materials and technology," said SiliconPipe executive Kevin Grundy. "It's time to stop fighting harder and harder to accomplish the next incremental improvement, and to sit down and re-evaluate how we should do the channel."

In particular, Grundy took issue with the work going on within Jedec to integrate a high-speed serializer/deserializer (serdes) into conventional dual-in-line memory modules to form a serial-I/O DIMM. "This is supposed to result in a fast, multipoint serial link between the DIMMs and the memory controller," Grundy said. "But it is a huge undertaking, both on the DIMM and on the controller ends."

Grundy said that the ability to move 3.2 Gbits/s minimum between controller and memory packages with existing driver/receiver technology, and without the use of serdes devices, was achieved with a substantial array of technologies.

They include differential receivers, CML transmitters and a proprietary shielding scheme that runs all the way from the pad ring on one die to the pad ring of the next.

That would allow the company to make a direct connection between a memory controller and a simple multiplexer chip, which in turn would be connected to a bank of DIMMs. Grundy said that the scheme could support up to 32 DIMMs at 3.2 Gbits/s per pin, while considerably simplifying motherboard layout and yielding precisely predictable performance.

To achieve it, SiliconPipe would need to make modifications to the drivers and package of the memory controller, modify the circuit board technology and develop the multiplexer chip, but with no changes to the DIMMs themselves-a considerably smaller effort than the Jedec serdes approach, according to Grundy.

But wait, there's more, as they say. Grundy claimed that by incorporating SiliconPipe technology in the DRAM chips as well, the company could produce a new kind of DIMM that could talk directly to the memory controller-again, across SiliconPipe-design channels-at up to 24 Gbits/s per pin. The connection could provide bus widths up to 128 bits, with no serdes and with a simple, differential, source-synchronous interconnect scheme.

SiliconPipe is demonstrating the technology at various performance points and is ready to discuss use of the IP with memory or core-logic vendors.