Over the last three to four decades, signal integrity has generally been seen as a set of issues, disparate in nature but sharing a common trait: unwanted noise that may wreck a design in some unsavory way. Starting from analog, and now a nightmare for digital designers, signal integrity has proved itself enemy No. 1 for many.

Power grid noise, crosstalk among various types of signals and electromigration can result in anything from lower time-to-failure to a design that is impossible to converge. Because signal integrity issues affect chips in fast-growing markets, they can limit yield and profits, and are becoming more difficult to deal with every day.

As technologies at 70 nanometers and below approach the mainstream, some signal integrity issues will move under the radar as they are handled and seamlessly integrated into the design methodology. This integration, however, will not diminish their importance.

Dealing with signal integrity generally involves trading off issues dealing with the following areas: some kind of performance (speed, power or area); yield or reliability; and design productivity. For example, guaranteeing a strict IR drop bound in the power grid may require substantially more power-planning runs and thus affect design productivity.

So what will affect signal integrity at the next three or four CMOS technology nodes?

- Growth in analog/mixed-signal components. Perhaps the most underserved electronic design automation segment (although certainly not underdiscussed), these designs are appearing in ever- more chips, especially in higher-growth areas such as communications and consumer electronics. Unfortunately, signal integrity issues tend to get exacerbated in these circuits. Imagine a power-management circuit that does not account for coupling, supply noise and electromigration.

- Consolidation of systems into single chips. Systems-on-chip (SoCs) with hundreds of cores are being sold for applications like high-end networking and will become a lot more common in the next few years. As a result, hundreds of delicate system-level signal wires roam over numerous third-party cores. These long wires may even display inductive and/or resistive effects not seen before.

- The increasing power of power. As if timing convergence were not enough, designs will also be increasingly closed on power constraints. So signal integrity management will not focus only on its impact on timing convergence.

- Increasing complexity of technology space. Designers will be given an increasingly rich technology arsenal, including integrated voltage islands, specialized cell libraries and wider (multithreshold) device choices. A richer set of options, unfortunately, also translates into more opportunities for signal integrity phenomena to show up.

- Manufacturability. Resolution-enhancement techniques and their integration in design flows will accelerate, causing new signal integrity modeling challenges.

These signal integrity issues will be addressed with a combination of technology, clever design and methodology restrictions. Different target markets will require different methods. But here's the catch-we can't add an extra loop to the design flow. The timing-convergence loop is already devastating. Fortunately, signal integrity can often be folded into the speed or power-convergence loop.

Thus, addressing signal integrity issues will be difficult, yet feasible. First, sophisticated signal integrity-mitigation design techniques will be used, perhaps borrowing ideas from high-speed, off-chip serial interconnects. Second, detailed signal integrity issues will be transparently embedded in conventional tools like timing analysis. Third, the use of new high-level tools such as power grid planning will increase substantially.

Finally, signal integrity information will be explicitly added to intellectual-property core generation: VSIA committees have had a role here, and are now in their third phase of signal integrity technical specifications for SoC designers.

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