Changes that are expected in SystemVerilog 3.1a include improvements in global declarations and separate compilation, a broader assertion capability, a functional coverage metric, an extended Verilog Procedural Interface (VPI), and semantic consistency with Accellera's Property Specification Language (PSL). Also on tap are technology donations from EDA startup Bluespec Inc., which is developing a high-level synthesis product based on SystemVerilog.

Dennis Brophy, Accellera chairman, said the purpose of releasing SystemVerilog 3.1 was to get user and vendor feedback. "The users felt we fell short on what should be in the language," he said. "They told us what they needed, and we've done that."

Brophy acknowledged that the changes went beyond what was originally expected, but he said they'll result in a better standard. "I think it [3.1a] elevates and improves the automation of verification much more significantly than what 3.1 encompassed," he said.

Vassilios Gerousis, chair of Accellera's technical committees, told symposium attendees that Accellera plans to release SystemVerilog 3.1a to the IEEE in June 2004. He said PSL will follow later in 2004, and Verilog-AMS, a mixed-signal simulation standard, will go to the IEEE in 2005. Accellera's policy, he noted, is to "incubate, refine, and solidify" standards before taking them to the IEEE.

David Smith, chair of Accellera's SystemVerilog testbench extensions committee, noted that Accellera is working very closely with the IEEE 1364 working group to make sure that Verilog standards do not diverge. Both Accellera and the IEEE, he said, are working hard to maintain a consistent Backus-Naur Form (BNF) — that is, underlying grammatical formalism — between their respective Verilog language efforts.

Smith said the SystemVerilog 3.1 language reference manual (LRM) generated over 200 errata and extensions. In his view, the biggest change in SystemVerilog 3.1a has to do with packages and separate compilation.

Smith explained that SystemVerilog 3.1 includes a "$root" construct that provided global declarations, but ran into problems with separate compilation. 3.1a reduces the scope of $root to simply being an unambiguous hierarchical reference. 3.1a also adds "packages," which provide globally available declarations in a reusable form, and "compilation units," which are defined to support separate compilation.

A large number of additions in 3.1a have to do with testbench generation. Among them, said Neil Korpusik, co-chair of the SystemVerilog testbench extensions committee, is the addition of a functional coverage metric that helps users measure the progress of design verification. This, he said, allows the creation of reactive testbenches that can monitor functional coverage during simulation.

Korpusik outlined a number of other testbench enhancements for version 3.1a. These include fine-grained process control, random weighted case statements, dynamic queuing, built-in methods, stream generation, more effective constraints, virtual interfaces, and sequence event control.

Matt Maidment, a member of the SystemVerilog design committee, identified two more significant changes in 3.1a. One is the extension of memory system tasks to include SystemVerilog data types. Another is the use of operator overloading to enable the use of simple operators with complex SystemVerilog types.

He also described the two Bluespec donations. One is data structure called "tagged unions" that, he said, provide type safety and brevity, and make it easier to use formal verification. Another is a technique called "pattern matching" that, he said, can make code both concise and expressive.

Swapnajit Mittra, chair of the SystemVerilog C-interface committee, noted that version 3.1a brings full VPI access to all of SystemVerilog. Further, new extensions to the VPI give full access to waveform files, regardless of file format. "Each vendor will provide a library supporting this API for their format," he said. "As a user, you won't have to modify code; it will be portable from one simulator to another."

New extensions that support assertions were described by Faisal Haque, chair of the SystemVerilog assertions committee. One is an "assume" directive that lets a user tell the tool to assume a given property is true. Another is the extension of local variable usage. Finally, assertions can be used within functions in a procedural scope.

Harry Foster, chair of Accellera's formal verification technology committee, said his group has made substantial progress in aligning SystemVerilog assertions with PSL, which is a separate, formal property language. He said that SystemVerilog assertions are now semantically aligned with PSL, and that the languages don't have different semantics for the same syntax. The next task, he said, is to maintain the same syntax for the same semantics.

Presentations from the SystemVerilog symposium are available on line.