SystemVerilog is coming, and fast. Before you know it, we'll have a new Verilog language with far broader capabilities, more complex syntax and a whole new learning curve. Vendors are working hard to support the spec, even as it is being fine-tuned and approved by committees.

If you think this is just another glacially slow, incremental update, like Verilog 2001, watch out: You may get run over.

Accelerated schedule

Don't let the deficiencies of the venerable Verilog language or the disappointing pace of improvements over the years color your expectations for the future. SystemVerilog is designed to be fully backward-compatible with Verilog, while incorporating a host of new features by means of technology donations from such companies as Co-Design Automation and its parent, Synopsys Inc.; Verplex Systems, now part of Cadence; and Intel Corp.

Language Reference Manual v3.0, published in June 2002, finally implemented Verilog 2001, expanded data types and updated Verilog syntax to include arrays/structures and unions. Transaction-level modeling was supported by the interface construct, though improvements in this area are coming. Most Verilog simulator vendors have at least beta support for v3.0 available today.

The next candidate (v3.1final) was released in June 2003 and is undergoing standardization and approval by Accellera committees. This version features major improvements for verification, including classes, semaphores and mailboxes, random constraints, program blocks, clocking domains, assertions, and a DirectC interface. You can find the latest specifications and more details on the Accellera Web site (www.accellera.org).

While the use of donated technologies greatly accelerates definition and maybe even implementation of a spec, it raises concerns for the homogeneity of the language. The Accellera committees are aware of this and have spent time making proposed features that look and feel like Verilog. Meanwhile, there are major changes at hand, and the oft-repeated judgment of Verilog coders as hackers is going to die quickly.

For example, most Verilog bigots- and I classify myself as one-have dreaded what we saw as C++ style obfuscations in our "sacred but simple" language. While all that scary syntax is coming, SystemVerilog simplifies things greatly by use of safe pointers, automatic garbage collection and more.

There will be a steep learning curve for anyone with no programming skills outside Verilog 1995. Many such users will probably continue to code that way for some time. And yet, I think that even the diehards will be seduced by the more modern coding style and powerful extensions of SystemVerilog.

How you will likely perceive SystemVerilog depends on your job description. For the designer, the flexibility of new data types, arrays and structures -together with less ambiguous register-transfer-level (RTL) coding styles-will be an immediate hit. Interfaces to abstract I/O boundaries will further win early converts.

Verification staff may benefit the most, through enhancements that allow the use of Vera-lite coding techniques along with assertion-based testing, random constraints and true transaction-level modeling. Imagine being able to test a design at all levels of abstraction from the same high-level procedure calls. Is this really Verilog?

Management will enjoy the productivity benefits of a common language for design and verification. The complex transition from system model to implementation will be greatly eased.

The learning curve will have to be dealt with: Even engineers with higher-level language experience than Verilog will need to learn how to use the new features in the hardware design/verification environment.But unlike past Verilog enhancements, which took forever to show up and earned a ho-hum response when they did, SystemVerilog is here today in a very usable form.

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