SANTA CRUZ, Calif. — Two language proposals from startup Bluespec Inc., provider of a SystemVerilog-based "assertion synthesis" tool, have been accepted by the Accellera standards organization for use in the upcoming SystemVerilog 3.1a release, according to the company.
The proposals from Bluespec, tagged unions and pattern matching, are said to raise the level of abstraction for design and improve the expressiveness and readability of the SystemVerilog language. Both concepts have been used in other high-level languages.
The SystemVerilog 3.1a release will be presented to the IEEE by June 2004. It incorporates a number of changes from the current SystemVerilog 3.1 standard, approved by Accellera earlier this year.
In a recent presentation, Matt Maidment, a member of Accellera's SystemVerilog design committee, showed examples of tagged unions and pattern matching. He said that tagged unions are data structures that provide type safety and brevity, improve correctness, and improve the ability to reason about formal verification.
Pattern matching, Maidment said, is used with case statements, if statements, and conditional expressions. He said it improves brevity and readability, makes it easier to implement tagged unions without run-time checks, and improves formal reasoning.
Bluespec announced its plans to offer assertion-based synthesis in early December. The company is preparing a tool set that takes high-level SystemVerilog descriptions and generates synthesizable RTL, claiming to reduce the time it takes to produce a verified netlist by up to 50 percent.
