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DATE panels to address design issues








EE Times


MANHASSET, NY — The interplay between embedded software and hardware designers will get a fresh airing at next month's Design Automation and Test in Europe conference.

A panel labeled "HW designers implementing from Embedded SW: Bottleneck or gridlock?" is scheduled for Feb.17 at the DATE in Paris. The annual European conference addresses research and development activities in design technologies such as systems-on-chip and embedded systems.

Representatives from ST Microelectronics, Ericsson, Artisan Software, Synopsys and CriticalBlue will discuss the importance of implementation routes to hardware from embedded software and review current state-of-the-art solutions. Also to be discussed are the right solutions for future designs. With hardware and software designers becoming more closely connected in developing complex electronics products, a gap remains between what tools and methodologies are being used by each. Both disciplines continue to use distinct design methodologies and infrastructures to construct design flows. These flows have not fundamentally changed in a decade.

Panelists will debate what steps designers can take to increase end-user productivity while at the same time generating a sustainable business opportunity for vendors.

"This panel includes representatives from all the interested parties that are required to formulate a successful strategy for [software and hardware] migration," said panel chair Chris Edwards.

Panelists include representaives from EDA vendors, semiconductor and systems companies.

Two panels will look at pressing design issues. "Managing Design Complexity in 90-nm Technology" will include executives from Altera, Broadcom, Virage Logic, AMI, TSMC Europe and Tensilica. They will address the challenges and the design methodologies needed to achieve productivity at 90-nm design rules.

"Determining the Value of Test" panel will include executives from LogicVision, Advantest America, STMicroelectronics, HPL, and LSI Logic who will debate the merits of using test to help debug first silicon, as a basis for repairing chips during manufacturing and in the field and finally as an infrastructure for diagnosis and fault tolerance.

System-level design concerns that are now dominating the definition of new platforms for future electronic systems will be debated by another panel of executives from Monterey Design Systems, ARM, CoWare, IBM Microelectronics and Axis Systems. The executives will address the advanced solutions for sub-nanometer physical design and manufacturability and the move from the register-transfer-level to an electronic system abstraction level.











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