To Altera, that means ditching the one-size-fits-all four-input lookup table, the basic building block for the logic fabric used in most FPGAs today. This week, the San Jose company will announce that its high-end Stratix-II FPGA family will instead use a fabric with varying inputs, called the Adaptive Logic Module.

Xilinx is sticking with the four-input LUT, but diverges from business as usual in another way. Normally, larger and pricier FPGA devices are first in line for any process shrink. But instead of shifting its high-end Virtex-II product line to 90 nm, the company will cut its teeth on low-cost Spartan devices. "We wanted something that we could learn from quickly," said Sandeep Vij, vice president of marketing at Xilinx, here. The company expects to compile critical yield and defect density data from test wafers with smaller and more numerous devices.

The four-input LUT was long believed to strike the right balance of performance vs. cost. In reality, customer surveys revealed that the distribution of inputs is all over the map, with the highest distribution of inputs being five, according to Altera. In terms of efficiency, it became clear that FPGAs should be flexible enough to allow wider and narrower input functions, the company said. Going wide is a means of reducing the interconnect requirement and boosting performance, while using fewer inputs drives down the cost of the logic.

Another reason to overhaul the logic structure was to counter the growing problem of power consumption, particularly leakage current. This would have made it difficult to simply port the existing architecture to 90 nm and expect customers to use the same number of logic elements. What's needed, Altera said, is an architecture that could boost performance without an excessive power penalty.

"It got to be very complicated," said Erik Cleage, senior vice president of marketing at Altera. "You realize that you have to do an architecture that addresses both issues at the same time."

The Adaptive Logic Module used in the Stratix-II slices through a Gordian knot of conflicting data about the optimum size of logic cells. It has been known for years that as interconnect delays become longer than logic-cell delays, the optimum complexity of a logic cell increases. But at the same time, the more complex logic cells are, the more difficult it is to use them efficiently. In designs with complex logic generators and multiple flip-flops, many cells are used at only a fraction of their full capacity.

The initial attempt to solve this dilemma was the four-input lookup table. The so-called 4-LUT proved a good compromise for several generations. But in recent years it has become clear that FPGAs implemented in modern processes would benefit greatly from larger logic cells. Theorists have floated the concept of heterogeneous architectures: logic fabrics that include both compact 3-LUTs or 4-LUTs and much more complex cells. But such architectures are complex to design, and entail routing and timing problems.

Altera's own data, extracted from its library of customer designs, supports the value of heterogeneity. By examining logic cones, mapping them onto LUT-based nodes and sorting them by the number of inputs that would be best at each node, Altera found that the distribution of fan-ins was nearly flat between two and six inputs, with a nice peak at five.

The Adaptive Logic Module neatly solves this problem, providing at one stroke both a somewhat heterogeneous architecture and the ability to put larger and smaller cells where they are needed. The eight-input structure on the input side of the logic cell can be partitioned to implement a partially populated 7-LUT, a full 6-LUT, a full 5-LUT along with a full 3-LUT, or a pair of 4-LUTs. By pin sharing-a technique familiar to complex-PLD users-the device can be expanded to 5 + 4, 5 + 5 or a pair of partially populated 6-LUTs.

By splitting the LUT into two pieces and using them separately, Altera helps the problem of underutilization. The mapping software maps logic cones into logic cells, deciding how wide a LUT is needed at each node. Then the place and route software picks the locations for the cells, attempting to use up all the spare pieces of LUTs by placing two nodes in each partitioned cell. This may increase local routing density, as nets may have to hop a few cells over to find a spare 4-LUT, for instance. But it also increases utilization of the logic within the cells, Altera said. And having the wide inputs available when they are necessary dramatically reduces the nasty tangles of logic cells that implement wide-input functions in fixed architectures.

All of this mapping does place an additional workload on the synthesis tools. For that reason Altera has been working for some time with both Mentor Graphics Corp. and Synplicity Inc., helping the EDA vendors to develop tools for the Stratix-II architecture (see story, page 46).

Altera said the fruits of these changes will be a shift to more advanced design rules-more logic resources, performance and bandwidth-while using fewer logic elements. Altera plans to deliver six Stratix-II devices this year, ranging from 15,600 to 179,400 logic elements. They should be ready by the second quarter.

Similar defect density

Rival Xilinx is taking a much different approach in its shift to 90-nm devices. Beginning in January, the company began shipping two 90-nm members of the Spartan 3 family at a rate of more than 10,000 units per month, and said it is on track to deliver 200,000 units this quarter. Xilinx had to contend with several technical hurdles in shifting to the new process node, most notably in the etching step.

Still, the early ramp-up period has so far proved no different from earlier process shifts. "The defect density is really comparable to older generations such as 0.13 and 0.15 [micron]," said Vincent Tong, vice president of product technology at Xilinx.

Not everything has gone as planned, however. Originally Xilinx hoped to maximize its production output by qualifying Spartan 3 on 300-mm wafers, but then decided to work with 200-mm wafers in order to minimize risk. The company now expects to qualify the 300-mm wafers for 90-nm production by midyear. Xilinx said 50 percent of its total chip production comes from 300-mm wafers today.

Unlike Altera, Xilinx said it won't have to make any changes to the four-input LUT structures that make up its logic fabric, though it has already added muxes to its existing Virtex architecture to boost performance. The company is planning to introduce later this year a new kind of application-specific FPGA that segments function blocks into interchangeable columns instead of squares on a grid.