This one day program will consist of four sessions where executives will present their technical/business vision in the domains of design, automation and test. The four sessions will be comprised of one plenary executive lunch panel featuring the CEOs of the three largest EDA companies, and three sessions featuring executives. The session will offer attendees information about the vision and roadmaps of their corresponding companies from a business and technology point-of-view.

Program organizer Yervant Zorian, chief scientist at Virage Logic, has recruited keynoter Gregory Spirakis, Vice-President, Mobile Platforms Group and Director of Design Technology at Intel to talk on building silicon products in 65 nm and beyond.

With Moore's law continung for at least another decade technology scaling presents several manufacturing and design technology challenges that must be overcome to build semiconductor products in a cost effective manner. Spirakis will deatil existing challenges such as power and process variations, as well as warn about newer problems that may arise in integrating heterogeneous technologies such as RF, MEMS on the same die/package.

Moderated by EE Times' editor-in-chief Brian Fuller, the executives panel will consist of R. Blake, VP Product Planning, Altera; E.H.Frank, VP Research & Development, Broadcom; A Kablanian, President & CEO, Virage Logic; C. King, President & CEO, AMI Semiconductor; K. den Otter, President, TSMC Europe; and C. Rowen, President & CEO, Tensilica.

The session will allow the executives to address 90nm technology challenges and the design methodologies needed to reach the necessary productivity.

Dataquest's Gary Smith will moderate the executive lunch panel consisting of Ray Bingham, President & CEO, Cadence; Aart de Geus, President & CEO, Synopsys; and Wally Rhines, President & CEO, Mentor Graphics. Attendees will hear from the executives of these three largest EDA companies about their business perspective and corresponding R&D efforts, with some emphasis on the plans for "R" in the R&D.

Other executives in the afternoon on Tuesday will debate the value of test. Moderated by Peter Clarke, news director of the Silicon Strategies website, the panel will include V. Agarwal, President & CEO, LogicVision; N. Konidaris, President & CEO, Advantest America; P. Magarshack, Group VP, Central R&D, STMicroelectronics; C. Vandenberg, President & CEO, HPL; and R. Vashista, VP Technology Marketing, LSI Logic.

With the very deep micron technologies, the impact of test is widening from a screening technology to one that helps debugging the first silicon, to a basis for repairing chips during manufacturing and in the field, to an infrastructure for diagnosis and fault tolerance. The executives will debate the value of this test chain.

The last executive panel o the day is on "Advanced Solutions for SoC Design". The following comprise the panel: J. Benkoski, President & CEO, Monterey Design Systems; M. Muller, CTO, ARM; A. Naumann, President & CEO, CoWare; T. Reeves, VP & GM, IBM Microelectronics, ASIC Division; and S. Wang, VP Strategy & Bus Dev, Axis Systems.

With system-level design concerns now dominating the definition of new platforms for future electronic systems, EDA tools need to address on the one hand the sub-nanometer physical design and manufacturability challenges, and on the other move from the register-transfer-level to a higher level of abstraction, the electronic system level. The executives in this session will address the advanced solutions to achieve both.