Data rates up to 3.2 Gbits/second and beyond-with rise and fall times in the picosecond range-present many challenges to preserving signal integrity when routing bits across high-speed backplanes. In particular, switching signals in high-speed optical networks requires high levels of flexibility, signal integrity and throughput.
So until all-optical switching and processing emerges from the laboratory, today's electronic digital crosspoint switches, if designed properly, serve as the best practical way to handle packet-, static- and circuit-switched high-speed optical networks. For example, existing digital crosspoint switches can carry broadband data streams without placing undue restrictions on the channel-to-channel skew and jitter for packet switching, while affording the protocol independence needed for static switching.
A typical networking chassis consists of a backplane that connects 10 to 16 line cards and one or, in the case of a redundant system, two switch cards. The backplane is characterized by the number of traces, trace lengths, board material and connector quality.
Of these, the number of traces determines the number of backplane layers. More layers lead to thicker backplanes, which in turn lead to longer vias. Long vias in high-speed backplanes behave like unterminated stubs and will degrade the signal integrity. To reduce the number of traces on the backplane, system engineers run the backplanes at higher speeds, helping them to reduce the number of layers. However, high-speed serial links will introduce a new set of problems, including intersymbol interference and signal attenuation.
Within a digital switch, input equalization, output preemphasis and output-level programming are among the techniques used to improve the signal integrity on backplanes with long traces and high data rates. Specifically, input equalization helps to compensate for intersignal interference on the incoming data stream, output preemphasis compensates for high-frequency loss in the transmission line and output-level programming adjusts the signal gain. Output-level programming gives the system engineer the option of launching signals with a higher peak-to-peak differential voltage for longer traces, or a lower peak-to-peak differential voltage for shorter traces, thus reducing I/O power whenever possible.
The switch card connects one ingress line card to one or more egress line cards. A few applications, such as circuit-connected applications in optical networks, require a switch to provide connections between line cards, generally with an external CPU configuring the crossbar switch. This is called out-of-band configuration mode and the switching is called static switching. In these applications, the crossbar configuration update time depends on how fast the CPU can write to the configuration registers, which is typically in the range of several hundred nanoseconds to a few milliseconds.
Other applications switch very small cells throughout the switch fabric and require fast switch reconfiguration. A cell consists of two portions: the payload, which carries the data, and the header, which carries the configuration data telling the switch how to route the cell.
The switch configuration changes every cell time, which is called dynamic switching and requires information-carried as part of the cell header-to change the switch configuration on the fly without losing any data. Designing a generic switch that can be used in both static and dynamic switching becomes more complicated when the cell size can vary with the application, from 64 bytes to 4 kbytes.
An ideal switch will provide both dynamic switching for establishing short-duration connections to switch cells and static switching for longer-duration circuit-switching applications in a single chip, programmable on a port-by-port basis to support both modes at once. The arrival time of cells into the switch can vary based on jitter and trace-length differences between line cards. Internal FIFOs are necessary to absorb the channel-to-channel jitter and skew.
Two other design concerns are port count and port data rate. Depending on the application, the number of ports can vary from 16 to 160 per switch, with 32-port switches most common. A typical port data rate is 2 to 3.2 Gbits/s, a range that accommodates several standards such as Sonet OC-48, 10-Gbit Ethernet, Fibre Channel and Infiniband.
In the ADSX34 34-port synchronous crossbar switch from Analog Devices, each port can be programmed for either in-band or out-of-band modes. It accommodates dynamic and static switching on a per-port basis and supports both cell and circuit switching. Further, power consumption can be reduced by turning off unused ports or modules that aren't needed in an application.
Herman Eiliya is a senior applications engineer for Analog Devices Inc. (Wilmington, Mass.).
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