The only paper to fabricate an actual device came from HP. Researchers there used nanoimprint techniques to create what they described as the world's smallest rewritable non-volatile memory: an 8-by-8 crossbar sandwich with an active molecular layer caught between two layers of electrodes. The device size, if scaled up, would result in a 6.4 Gbit/cm² bit density.

Nanoimprint technology was relevant because the electrode fingers, 40 nm wide and set on a 130 nm pitch, were created by mechanically impressing their pattern on a novel receiver material. This material, formed by dissolving a polymer in its related monomer, permitted low-temperature (70 deg.C) and temperature (500 psi) impression while retaining the very high-resolution pattern. The material was used as the resist for an etch step that subsequently formed the metal fingers in a Pt/Ti bilayer.

In the following paper EV Group (Scharding, Austria) described a quite different process using hot embossing. In EV's process a Si or Ni stamp is bonded to a stronger substrate, then used at high temperature to emboss a polymer layer on a wafer of up to 200 mm diameter. A non-stick layer eases separation after pressing without damage to either stamp or the pattern in the polymer. The paper presented results on high-aspect-ratio features finer than 100 nm, and described work on an optical alignment system.

Following this, two papers each from equipment/materials vendors Nanonex Corp. (Princeton, New Jersey) and Molecular Imprints, Inc. (Austin, Texas) described the gradual maturing of their respective technologies.

Nanonex is pursuing a two-layer approach in which a thin (60 nm) top layer of polymer is mechanically imprinted with a mold. The pattern in the polymer is then fixed with ultraviolet light exposure, and thinned areas are removed with a reactive-ion etch.

This forms the polymer layer into a resist mask, which is then used by a second reactive-ion etch step to pattern an underlying layer. This more robust 200 nm layer can then be used as the resist layer for a more aggressive etch or deposition process, or it can be stripped and itself used as a component in a micromechanical device.

Because of the two-layer approach, Nanonex claims, the process is inherently low-temperature and low-pressure — the company cited 20 psi. The company claimed that a 200 nm grating had been accurately reproduced in the bottom resist layer using the process.

As in other nanoimprint processes, Nanonex has identified uniformity of pressure and correct alignment as key issues. They claim to have solved the pressure problem by not using a hard platen behind the mold. And the company said that their equipment could be used with conventional alignment machinery.

Molecular Imprints, for its part, described its step-and-flash process, which also uses UV to cure the polymer. The material in this case is a low-viscosity liquid that is dispensed as the device steps, rather than spun on before the imprinting step. A fused-silica template coated with release agent is then pressed into the liquid, and UV exposure is made through the back of the template. After release, residual material is etched away.

MII claims to have reproduced features in the 20 nm range with the process, but these papers described "sub-100 nm" pillars and contact holes. The company claims that materials now developed can survive more than 2000 imprints, or about 25 200mm wafers, without developing systematic defects.

Clearly significant work remains to be done in defect characterization, materials choices, alignment and full-wafer yield on all the processes described. But the progress to date, lying as it does outside the mainstream of R/D funding, raises the possibility that by the time 193 nm immersion lithography runs out of steam, it may be feasible to use nanoimprint techniques to pattern resist for the most critical layers.