Altera Corp. announced the development of a parameterizable PCI_B Master/Target core through its MegaCore program. The core supports 32-bit, 33-MHz PCI applications and is compliant with the Peripheral Component Interconnect Rev. 2.1 spec.
Tapan Mehta, senior product marketing engineer, said the internally developed core offers greater functionality, is more complex, and thus is a bit more challenging to implement than Altera's PCI_A core. Unlike the PCI_A, the PCI_B is parameterizable and has six base address registers with adjustable memory types and sizes.
The core uses approximately 1,050 logic elements in an Altera Flex10KE PLD and is available in two independently operated pieces: a PCI Master and a PCI Target. According to the company, independent operation of the pieces provides minimum latency, high flexibility and efficient use of the PCI bus.
The company said the core has been tested against most PCI host bridges, including the Intel 430FX, 440FX, 430VX and 440LX and the Digital PCI/PCI bridges.
Users can evaluate the core via the Web using Altera's OpenCore facility. It is priced at $12,995 and comes with full documentation, software drivers and sample test vectors.
Mehta said to expect Altera's OpenCore to release a 64-bit, 33-MHz PCI core and a 64-bit, 66-MHz PCI core in the coming months.
Xilinx Inc. has expanded its AllianceCore library with two cores aimed at enhancing Internet data security and bandwidth: a Data Encryption Standard (DES) engine core and an HDLC controller core to support the point-to-point protocol over Sonet (POS) communications standard. The two offerings are respectively available from AllianceCore partners Memec Design Services and CoreEl MicroSystems.
The XF-DES Data Encryption Standard engine, offered by Memec, establishes secure Internet transactions when employed in remote-access servers as well as satellite and cable and data modems. It supports both single- and triple-DES modes of operation. In single-DES mode, the core supports data throughput in excess of 155 Mbits/second (OC-3 speeds). It is certified by the National Institute of Standards and Technology.
CoreEl MicroSystems' PPP8 HDLC core is a part of the circuitry used to improve Internet bandwidth by packaging Internet traffic for transport over existing high-speed Sonet networks. The core conforms to the RFC1619 point-to-point protocol (PPP) over Sonet and RFC1662 PPP in the HDLC framing specification. It is delivered as two modules, supporting transmit and receive operations separately.
The PPP8 HDLC core can operate at speeds of up to 80 MHz on the Xilinx XC4000 FPGA family and at higher speeds on the new Virtex family.
Both cores are available in Xilinx net-list formats. XF-DES can be purchased directly from Memec Design Services for $5,000. The Verilog source-code version has a list price of $15,000, which includes a test bench. The PPP8 HDLC core lists for $22,000 and can be purchased directly from CoreEl MicroSystems. Source code is available at extra cost.
