Meanwhile, one of the EDA startups targeting system-level design will issue its own proposal at DAC. CynApps Inc. (Santa Clara, Calif.), headed by EDA veteran John Sanguinetti, will reveal its mission to provide C++ class libraries and related tools.

Named after the Rosetta stone that made it possible to decipher Egyptian hieroglyphics, the SLDL committee's first public proposal is a semantic framework that can map system constraints to multiple functional-description languages. Rosetta itself provides the syntax, while the actual semantics for the constraints are being developed by the Design Constraints Description Language (DCDL) effort, sponsored by Open Verilog International, VHDL International and the Virtual Socket Interface alliance.

Rosetta has already sparked some criticism from those who believe it's too close to VHDL, or who question the approach of bridging between multiple functional languages. Some startups, in fact, believe they have a single approach that can solve most system-on-chip design problems. In addition to the Cynlib library from CynApps, these approaches include the Superlog language from Co-Design Automation and a Java-to-RTL compiler from LavaLogic.

The reason for all this activity is simple. Register-transfer level (RTL) hardware design is too low an abstraction level to start designing multimillion-gate systems. What's needed is a way to describe an entire system, including embedded software and analog functions, and formalize a set of constraints and requirements — all far beyond the capabilities of existing HDLs.

"VHDL and Verilog both will become the assembly language of hardware design," said Sanguinetti. "You'll write RTL code for things that are performance-critical, but for everything else, you'll stop at a higher level."

The belief behind Rosetta is that no single language will ever be able to describe all possible aspects of system-on-chip design, said Steve Schulz, VHDL International's chairman. Thus, he said, the SLDL committee decided to come out with an "integration framework" that will leverage existing language technology and provide users with a formal way to map from one domain to another.

Phase one of the SLDL effort is the Rosetta constraint language and the actual constraints to be defined by the DCDL group. A Java-based parser for Rosetta is under development at the University of Cincinnati under Darpa contract. Both that and a Language Reference Manual should be available by the end of 1999, Schulz said. The first industrial use is expected by the end of 2000.

SLDL's second phase will bring in "perhaps four or five" functional languages to which Rosetta can map constraints, Schulz said. These could be existing system-level languages, such as SDL or Esterel; a programming language such as Java; or a new language or class library from a startup. Beneath those languages, VHDL and Verilog can still be used for hardware implementation.

Rosetta claims to be the only language that describes declarative design constraints at the system level, and to thus be non-competitive with any existing functional language. Rosetta will let users set constraints in such areas as timing, latency, power, cost, bandwidth and throughput, across such application domains as digital hardware, analog hardware, embedded software, and mechanical and fluidic devices that may be on- or off-chip.

Mixed reviews

"So far, I think it [Rosetta] is going to work," said Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.). "It's not competing with anything. Nothing else addresses the specification space. The reason for it is so you can get system-level designs out, and do it in silicon."

But Smith acknowledged Rosetta has caused some controversy. Some people objected when the SLDL committee joined VHDL International; others may find Rosetta syntax to be too VHDL-like. Rosetta is heavily influenced by VSpec, which was developed to bring formal constraints into VHDL. That orientation should be a plus in Europe but may be a "detriment" in the United States, Schulz acknowledged.

Simon Davidmann, president and chief executive officer of Co-Design Automation (San Jose), thinks the language's name reveals its shortcomings. "My understanding is that the Rosetta stone was pulling together antiquated languages," he said. "It's a couple-thousand-year-old PLI [programming language interface]. We're trying to remove the need for PLIs to glue things together."

Davidmann said that his company's Superlog can handle all of the functional and logical design requirements for systems-on-chip, including constraints. But he doesn't necessarily see Rosetta as competitive. "They could glue other things to us if they wanted to," he said.

Cary Ussery, president and chief executive of Improv Systems (Beverly, Mass.), sees another problem. "The real issues for embedded chip design are increasingly embedded software issues," he said. "By basing everything from the HDL approach, you're starting from the wrong point." Ussery's company is developing a new type of programmable architecture that will be customized mostly in software.

There are several different approaches to system-level design languages, and a clear winner has yet to be identified, said Dennis Brophy, chairman of Open Verilog International (OVI). While he believes the SLDL committee has a "very sound" approach, Brophy also noted that private companies are proposing such things as class libraries and embedding pragmas into software programming languages.

OVI is working with SLDL in the constraints area, but has not explicitly endorsed any particular approach, Brophy said. Meanwhile, he's not concerned that SLDL has become part of VHDL International — OVI, in fact, suggested that, Brophy noted.

The SLDL effort has taken some heat for "design by committee," but Schulz had a ready response for that. "We spent time in committees coming up with the requirements, but when we got to specifics the implementation was done by five or six people," he said. "That's as small as any startup." Major contributors include Perry Alexander, professor at the University of Cincinnati and creator of VSpec, and Dave Barton, SLDL chairman and senior computer scientist at AverStar (formerly Intermetrics).

Facets of design

Rosetta is comprised of programming units called facets. "You can think of a facet as a description of a specific part of your design, with respect to an engineering concern such as power," said Schulz. Facets support predefined domains, including monotonic logic, state-based, continuous-time, synchronous-reactive, discrete-time and finite-state. Facets include variables and predefined terms.

Facets also include predefined types, making Rosetta, like VHDL, a strongly typed language. "If you don't put in typing you lose semantic meaning," said Schulz.

When the characteristics identified in a facet are asserted in the design, the facet can become part of a "component." A component might be a DSP block in a system-on-chip, and its description would include certain characteristics of power, timing, function and cost. A "system" is a collection of components and facets.

Constraints will be defined by using a constraints domain, such as heat, power or timing. These domains will be defined by the DCDL effort. Requirements will be defined by such domains as logic, state-based and discrete time.

While Rosetta is designed to complement any existing language, VHDL and Verilog will have to "evolve" for translations from Rosetta to be meaningful, Schulz said. This may come about through such efforts as VHDL 2000 and the OVI architectural subcommittee. "But whether it happens or not, I cannot say," Schulz said.

Though not directly familiar with Rosetta, Sanguinetti is nonetheless skeptical of the overall SLDL approach. "Chances it will turn into something solid and useful are not very high," he said. "You can do everything using C++ and a class library that they want to do with a new language."

Sanguinetti, a founder of Chronologic Simulation, started CynApps last year under the name C2 Design Automation — which is how it will be billed at DAC. The company employs 12 people and has received around $1.8 million in venture funding from such well-known EDA investors as Andy Bechtolsheim, Gordon Bell and Rajeev Madhavan.

The new company's Cynlib is a C++ class library that supports hardware description, simulation and synthesis. "The neat thing about this technology is that there isn't any identifiable simulator," said Sanguinetti. "Simply compile the model with a standard C++ compiler, run the object and that's the simulation program."

C++ gets a vote

However, there does need to be a way to convert C++ code to RTL Verilog for synthesis, and that's coming in the third quarter, Sanguinetti said.

Sanguinetti argued that the best way to do system-level design is with a general-purpose language and that C++ is clearly the best choice. That's because it's extendible, he said, and notions such as concurrency can be easily represented in class libraries. The object-oriented nature of C++ corresponds well to HDL hierarchy, Sanguinetti added.

Java is the "next best" choice, he said, but it doesn't support templates or operator overloading, resulting in a need for numerous procedure calls.

"One of our goals is to try to make this as short a step from Verilog as possible," he said. "This can look just like a Verilog dialect of C and is really quite easy to learn." Another feature, Sanguinetti noted, is that users can create classes to implement reusable functions like FIFOs or protocols.

CynApps plans to make the specs for Cynlib public and has offered Cynlib to OVI's architectural committee, Sanguinetti said. It meets Wednesday (June 23) at DAC.

Rosetta will be introduced at a "birds of a feather" session Wednesday (June 23) afternoon at DAC.