Chronology's announcement comes on the heels of an effort by testbench market leader Verisity Inc. to establish its proprietary "e" language as a standard in the testbench field.

To date, testbench generation tools from Verisity (Mountain View, Calif.), Synopsys Inc. (Mountain View) as well as Chronology (Redmond, Wash.) have required users to learn and then describe testbenches with proprietary languages. But the Chronology effort aims to allow verification engineers to generate testbenches with the same language that design engineers use to describe system-on-chip architectures.

The two rival languages Chronology plans to support, SystemC and CynApps, are viewed as the top two candidates for the next design language. Michael Meredith, vice president of technical marketing at Chronology, said that the company is supporting both languages and is not taking sides.

"We are supporting both efforts because we are not in an effort to predict which of those languages will be the most successful," said Meredith. "We are going to provide testbench automation support for any design environment that looks like it will be successful enough to have a bunch of EEs in front of it."

Meredith said Chronology is announcing the strategy before it has product to counter a recent effort by rival Verisity to have its proprietary e language codified as the standard language for testbench generation through the Open Verilog International standards group, now known as Accellera. Verisity's move garnered wide praise when it was announced last month.

Verisity's SpecMan Elite is the market share leader at 77 percent, followed by Synopsys' Vera with 19 percent and Chronology's QuickBench with 4 percent, according to 1999 figures from research firm Dataquest Inc.

"It is ridiculous to standardize on a language when this segment of the market is so young," said Meredith. "Testbench generation tools have only penetrated 4 percent of the overall market so there is a lot of innovation left to do in this area."

Meredith said that the QuickBench environment lends itself to adapting to new languages and that if other system languages emerge, the tool should be able to support them. "Because of our versatile architecture it makes more sense and [is] easier for us to support these new languages," said Meredith. "It doesn't make as much sense for the other vendors — if you peel our language out, there is something left."

Meredith said, however, that if Verisity's e language does become a standard, that QuickBench could also support it.

Thwarting of C?

Gary Smith, chief EDA analyst at Dataquest (San Jose, Calif.), said that users really like the idea of using C and C++ languages for modeling and that the whole idea behind Verisity's effort to establish the e standard was to thwart the use of C and C++ for modeling.

"SystemC started out as a modeling language standard, which makes it a natural for being the testbench development language," said Smith. "I'm hearing some good reports from users. That meant Verisity had to react fast to establish e as the standard." In Smith's view, "There's still another shoe to drop, so it'll be interesting to see how this standard develops."

Meredith said that customers want to use the C-based languages for architectural design but are even more interested in using C-based languages for high-level verification.

"Verification is still the biggest bottleneck in the overall design process today," said Meredith. "So users are really screaming for easy-to-use verification tools to speed up the process."

The QuickBench verification suite has an autolink capability to create bus functional models (BFMs) by capturing timing diagrams and adding Verilog and VHDL. Meredith said the new version of QuickBench, to be launched by year's end, will be able to add SystemC and CynApps as well. The tool will allow customers to generate BFMs and transactions with SystemC, CynApps or Rave. The tool currently generates Verilog and VHDL and the future version will also output SystemC and CynApps.

"We will allow customers to use SystemC, CynApps and Rave at the same time in the same simulation," said Meredith. "We think this will make it a less traumatic transition for our current customers but also allow customers to use what they have today while they move into one of these C++ environments."

Swami Venkat, product marketing manager for Vera at Synopsys, said that Chronology is not alone in supporting SystemC and that Synopsys also plans to use it as an implementation language in an upcoming version of Vera.

SystemC supported

"Synopsys' Vera will support SystemC implementation," said Venkat. "This will expand Vera's role from being used at RTL and gate level to architecture and system modeling. SystemC implementations can be verified using Vera for describing the verification environment and creating self-checking stimulus."

Francine Ferguson, vice president of marketing at Verisity, said that the current versions of SystemC and CynApps don't have the hardware constructs necessary for in-depth hardware verification. She said the company has in the past, for particular customers, configured the SpecMan Elite tool to run with C.

"For us it is not a question of can we support C-based languages, it is a question of which is the best language for testbench automation tools. Users get better results with e and that is because of the way it works with SpecMan Elite's engine. If I were losing in this area I would jump on the C bandwagon, too."