Assertion monitors, also known as event monitors, are short HDL routines used to check for specific types of bugs. Many users write their own to check for conditions such as bus contention. Now, with Verplex's Open Verification Library initiative, designers are invited to freely use any of the monitors at the library's Web site and to contribute their own.

Verplex is hoping that some of these users will buy Black Tie, a tool that promises rapid, exhaustive verification of assertion monitors on designs with millions of gates. But the monitors can also be used with existing simulators, and Verplex's library initiative has already gained support from several other EDA vendors.

"This library can change the way verification is done," said Dino Caporossi, director of marketing for Verplex, based here. "It's a different approach, but it uses something that everybody already understands."

The eventual intent is to turn the library over to an independent standards organization, Caporossi said. Backers of the Open Verification Library initiative include Axis Systems, Chronology, Co-Design Automation, Denali Software, Hewlett-Packard, Magma Design Automation, Novas Software and Ricoh.

Missing list

Missing from this list, however, are the four largest EDA vendors: Cadence, Synopsys, Mentor Graphics and Avanti. All compete with Verplex in the formal equivalency-checking market, and collectively, these four vendors claim the lion's share of the HDL simulation market.

The methodology behind the library was originally developed by Harry Foster, senior member of the CAD technical staff at Hewlett-Packard Co., and detailed in a book he co-authored with Lionel Bening, Principles of Verifiable RTL Design, published by Kluwer Academic Publishers.

As of Monday (Nov. 20), Verplex is launching its Open Verification Library Web site with 21 monitors. The site includes a download area, submission area, full documentation and a discussion group. Most monitors carry names that describe their function, like "assert_always," "assert_no_overflow" and "assert_odd_parity."

An upload area will let Verilog users add or customize monitors. "This library was conceived by the user community and will be driven by the user community," Caporossi said.

"The trouble with any new verification tool is that the design engineer must spend a lot of effort developing the scripts needed to drive the tool," said Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.). "The open-source library was a brilliant approach to solving that problem."

"The notion of sharing assertions, so people don't have to write them on their own, is very powerful," said Scott Sandler, president and chief executive officer of Novas Software, a provider of HDL debugging software.

Monitors today are written using many different methods, and some cannot be accelerated by Axis Systems' hardware verification engine, said Steve Wang, Axis' vice president of marketing. "By having a standard, Axis can accelerate simulation of all assertion models," he said.

Black Tie promises a new way to verify designs using assertion monitors. Compared with simulation, its main claim to fame is speed and capacity. In one customer benchmark, Verplex claims that Black Tie verified 5,724 user-defined monitors in a 2.4 million-cell design in 18 minutes on a single Unix workstation.

Input to Black Tie consists of Verilog or VHDL code, preferably at the register-transfer level, although gate level is permissible. Users can write assertion monitors or get them from the open-source library. Black Tie also comes prepackaged with monitors for common error conditions such as bus contention, dead-end states, simultaneous sets and resets, asynchronous clock domain crossings and stuck tristate signals.

If a monitor doesn't pass, Black Tie enters its debugging mode, and provides highlighted source code and a counter example. A small simulator within Black Tie allows waveform viewing, and users can take a standard VCD file to any Verilog simulator.

Designers shouldn't conclude they can carelessly write monitors, however. "It's just like simulation," Caporossi said. "If you write an assertion monitor that needs to verify hundreds of millions of vectors, our tool can't handle it either. If you stick to monitors that are time-bounded, you can definitely do full-chip verification."

Some of the principles behind Black Tie were described in an International Test Conference 2000 paper entitled "Static property checking using ATPG vs. BDD techniques." Authors from Verplex and the University of California at Santa Barbara described a methodology that combines automatic test-pattern generation and binary-decision-diagram techniques.

Black Tie is shipping now on Unix or Linux systems starting at $75,000.