Commercial microchips work well in their intended environments, but generic microchips will not function correctly if exposed to the high doses of ionizing radiation that satellites encounter in outer space. Modern CMOS circuits must overcome three specific concerns related to ionizing radiation: total-dose, single-event and dose-rate effects. Minority-carrier devices such as bipolar transistors, optical receivers and solar cells must also deal with recombination-generation centers (caused by displacement damage), which are not major concerns for majority-carrier CMOS devices.
Making CMOS components more resistant to radiation-the process known as radiation hardening-requires both changing designs and altering manufacturing processes.
Ionizing radiation breaks atomic bonds to create electrons and holes in semiconductors and insulators. In the insulator silicon dioxide, the electron mobility is greater than the hole mobility. Thus, many electrons are rapidly collected outside the insulator, while more of the slower-moving holes can get trapped at defects in the oxide or at interfaces. An excess of trapped holes creates a positive space charge, which can accumulate n-type surface layers or invert p-type surface layers. Those space charges lead to the formation of parasitic conducting paths independent of gate control.
To harden against total-dose effects, one must reduce the formation of a net space charge in the oxides. One either traps fewer charges-for example, by making the layers so thin that fewer holes are created and subsequently trapped-or finds ways to trap equal amounts of electrons and holes to reduce the net space charge.
Because scaling laws demand thinner gate oxides as transistor dimensions shrink, hardening gates oxides is a lesser concern for modern technologies. Instead, charging of the thicker isolation oxides becomes the major total-dose concern.
Several process and design variations can reduce charging in insulators. They include reducing mechanical stress in the oxide, lowering the electric fields across the oxide, increasing the parasitic threshold voltages of the underlying surface layers and reducing ion-implant damage in the oxides.
By applying those lessons, Sandia has hardened shallow-trench isolation to more than 5 Mrad(Si) of total-dose hardness. In addition to process variations, design alternatives that mitigate against total-dose effects include NAND rather than NOR logic, low fan-in gates and wider design margins.
Error correction is a standard design approach for protecting commercial circuits from single-event effects, but it requires extra transistors and adds to the total chip area. Two different process techniques can prevent the single-event-generated excess charge from altering a logic state. One way is to slow the write time of memory cells-for instance, by adding feedback resistors in RAM cells and latches, such that the excess charge is sunk to ground during a single clock cycle.
Alternatively, one can reduce the amount of charge collected at the node through the use of an insulating barrier that is under the transistor-silicon-on-insulator, or SOI, technologies.
These performance and hardening advantages of SOI come at the cost of creating total-dose concerns for the buried insulator. Achieving total-dose hardness for SOI requires preventing the formation of space charge in the buried insulator under the conducting channel that would shift transistor thresholds, and thereby alter timing and prevent using dynamic latches.
Nuclear survival
Single-event and total-dose effects represent the major concerns for satellites in the natural radiation of space. They are also the major concerns for satellites that must operate in orbits whose radiation environment is pumped up by high-atmosphere nuclear detonations. However, one more effect is important for strategic systems-those that must survive line-of-sight exposure to a nuclear detonation.
Such systems and the chips within them must accommodate massive photo-generated currents, because in essence each p-n junction in the circuit acts like a solar cell. The first line of defense is to collect less total current. A straightforward way to reduce the photocurrent collection volumes is SOI. It's also helpful to design wide power buses to maintain voltages in the center of the chip.
Radiation hardening limits design options. Hardening a microprocessor as complex as Intel's Pentium is a major undertaking. Achieving the required radiation immunity means making changes at the logic level and modifying how the functions are implemented at higher levels of the architecture.
Given this insight, it comes as no surprise that high-volume commercial manufacturers are unwilling to accept the penalties associated with enhancing the radiation immunity of their products.
