In addition to improving the volume, reliability and yield of compound semiconductor manufacturing, the technique could eventually allow the integration of compound semiconductor regions within a silicon die, and the integration of efficient RF and optoelectronic circuits on the same die or substrate with digital silicon-based circuitry.

Although Nitronex Corp. (Raleigh, N.C.) has managed to grow gallium nitride on silicon,

The researchers are now looking at developing a way of making indium phosphide (InP) on silicon to cut the cost of optoelectronic devices.

"The cost advantage will definitely come from the optoelectronic area. It will also benefit more from higher levels of integration," said Padmasree Warrior, general manager of a subsidiary that Motorola has formed to commercialize and license the compound-semiconductor-over-silicon technology. The first step is to produce cheap GaAs wafers, but Warrior said work is ongoing to demonstrate the technique's viability for driving integration to the system-on-chip level.

Interstitial layer

The technique that Motorola used to form GaAs on top of silicon makes use of an interstitial layer to absorb the differences in the pitches of the crystal lattices. Originally, the team used a perovskite, strontium titanate (STO) dielectric layer, to build ultrathin transistors. During this work, the researchers discovered that oxygen tended to leak into the silicon underneath, forming an amorphous layer.

That caused problems in a silicon transistor, but Jamal Ramdani, a Motorola Labs researcher, said he thought the effect might be useful as a way of putting compound semiconductors onto a silicon substrate. The amorphous layer allowed the perovskite to relax to its own normal crystal lattice form. As this lies between the forms of silicon and GaAs it serves to take the strain and avoid the cracks and dislocations that result from trying to join mismatched lattices.

By modeling the bonds formed between GaAs and STO, the team created a recipe for depositing GaAs. IQE used molecular-beam epitaxy to build the layers up to sufficient thickness.

"The GaAs layer is thick enough to function as standard GaAs," Roberson said. "There is no difference whatsoever [compared with bulk GaAs] and there is no goal to make it electrically different.

"There is also no advantage to making it hugely thick," he said. "Thinness is part of the cost structure. The thinner you can make it, the faster you can deposit it."

To build InP wafers, Roberson said Motorola will need to use a different interstitial layer but it would be another perovskite.

"We would need different materials but the science is the same. The technology is extendible to any of the III-V materials," he said.

Warrior said Motorola's new subsidiary will license the technology across a number of sectors and is looking closely at optoelectronic and lighting applications, which typically use GaN grown on sapphire today. However, through a deal with Nitronex, Microsemi Corp. (Irvine, Calif.) is marketing blue LEDs using GaN on silicon. Separately, Cree Inc. (Durham, N.C.) offers LEDs that use GaN on silicon carbide.

"The business model we have is to license the technology broadly. We will start in the early part of next year," Warrior said. "We intend to work closely with IQE. Working with IQE brings a lot of value to the commercialization."

A spokesman for IQE said the company is considering whether to license the technology from Motorola to make its own compound-semiconductor-on-silicon wafers.

"Our involvement has been the commercialization process — proving that the technology can be produced on 8- and 12-inch wafers. We are looking at all the commercialization routes. Licensing [the technology from Motorola] is one of a number of options. We believe it is a significant development. We are now looking at how to progress with InP."

Chris Edwards is editor of Electronics Times, EE Times' sister publication in the United Kingdom.