There's been a lot of noise in the press lately about the use of C++ for the next generation of chip design. The idea is that in the near future, simulation, synthesis, timing and your system's software will all be written in C/C++, with a blithe blurring of the lines between the portion of your design that is ASIC-based and the portion comprising microprocessors running software. You know-systems-on-chip, virtual prototyping, hardware/software codesign and all that hokum.
To attract the first converts, companies promoting this idea are offering C++-to-Verilog translators or hardware-oriented C++ class libraries. Click on Synopsys (www.synopsys.com), CynApps (www.cynapps.com), C-Level Design (www.cleveldesign.com) or Frontier Design (www.frontierd.com) to peruse those approaches. Beyond translation are such hardware/software codesign standbys as Synopsys' Eaglei, Mentor's Seamless (www.mentorg.com), CoWare's N2C (www.coware.com) and Summit's V-CPU (www.summit-design.com) tools.
Either way, they all effectively promise those happily blurred lines between the ASIC and microprocessor portions of your system, with the added promise that everything, even your ASIC, can now be designed in lightning-fast-to-simulate C++. Joy!
But there's a fly in this C++ ointment nobody's talking about. To borrow from an old adage, there's not much new under the EDA sun.
Most of what you see as "new" commercial EDA software today typically is a rehash of something that was conceived in an internal CAD department years ago at IBM, Siemens, Bell Labs, Motorola, Sun, Intel, GE or Xerox. And, yes, those guys tried designing hardware with C.
"Try using the C/C++ EDA tools, and you will quickly see what they can and cannot do," Geir Hedemark of the University of Oslo posted on comp.lang.vhdl. "The company I work for has used high-level synthesis tools for a long time. So far, no C/C++ tools can provide what we need."
John Reynolds of Intel quickly replied, "I agree with Geir. Evaluate some of the tools and you will quickly see how restricted you are and the things you cannot model.
"The observation that one engineer had around here when discussing the C/C++ vs. HDL argument was that the more you restrict C++ by using class templates, etc., the more you shave the language so that you can synthesize it, the more funky crap you add into the language to simulate concurrency already found in HDLs, [the more] your 'language' approaches a Verilog or VHDL!"
So, in a nutshell, since VHDL is hardware Ada and Verilog is hardware C, it appears that we'll being going back to the future when we walk down the C++ path to hardware design.
Verilog++ ?
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract ASIC Designer, and loves hearing from engineers at jcooley@world.std.com or (508) 429-4357.
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