If you want to know how the five-way physical-synthesis horse race is going, you've got to track what the engineers who actually use such tools are saying and, more important, the bugs they find. (You can find such talk in newsgroups, on ESNUG or wherever engineers hang out.) Everything else is fluff designed to woo Wall Street and the more gullible EDA buyers.
Engineers who actually use a tool will have some praise and lots of gripes. It's human nature. No software is bug-free. When you're seeing lots of public bug talk about a tool, you truly know that it's being widely used. When you see only public smiles and sunshine about a tool, be aware that you're the one being used.
Having said this, here's the status of the RTL-to-GDS-II race as of early February. With the exception of Synopsys and Monterey, most of the EDA vendors (Cadence, Avanti and Magma) seem stuck in taxicab mode with their physical-synthesis tools. Taxicab mode is where the EDA vendor provides both the software and its own engineers, to drive the software at the customer site. It means the software is too unstable for real customer use.
Most of the 70 big-money EDA customers are buying only evaluation copies and holding private taxicab races-which is why I laughed when newbie Cadence CEO Ray Bingham bragged in a Jan. 25 press release about the company's PKS having 11 new "customers." Bingham's hotel-finance background, and his lack of any engineering experience, shows here.
The big breakthrough happened three months ago, when a real chip designer, Bob Prevett of Nvidia, wrote a detailed technical review in ESNUG 335 of PhysOpt (now called Physical Compiler) from Synopsys. A week later, Matrox and Nvidia both announced they had done chip tape-outs with Physical Compiler.
Then another real chip designer, Jon Stahl of Avici, wrote a detailed technical review of Synopsys' Chip Architect in ESNUG 338. That meant Synopsys was clearly moving out of taxicab mode.
Cadence PKS was believed to be struggling with three conflicting timing engines among PKS, Qplace and Pearl. Then, in SNUG 342, Jay McDougal of Agilent reported only a 0 to 3 percent timing error among PKS, Qplace, Pearl and even PrimeTime. (McDougal's short comment is the first known actual-customer usage statement about PKS.)
Avanti and a very noisy Magma are playing up vague customer endorsements , but nothing verifiable, in the press. Monterey's just a town in California. These are still taxicab companies. So, with two customer tapeouts vs. a first customer mention, it appears that Synopsys is about six months ahead of Cadence in physical synthesis. Watch the bug talk to see whether Synopsys stays ahead or falls behind.
John Cooley runs the e-mail Synopsys Users Group (ESNUG), is a Contract Asic Designer and loves hearing from engineers at jcooley@world.std.com or (508) 429-4357.
