It's fun to watch a point tool grow up right in front of your eyes. After last year's DAC, Kristie Armentrout of Tektronix wrote to me about ClockWise. "John, I thought Ultima's ClockWise was pretty cool. This is a clock tree synthesis tool that uses clock skew to fix timing problems. If a flip-flop has tight timing on one side and relaxed timing on the other, ClockWise will try to move the clock edge toward the relaxed side," Kristie wrote. "It takes in DEF, a Verilog netlist, .lib, LEF and PrimeTime timing constraints. It does a routing estimation and then inserts the clock tree buffers and returns a DEF, a revised netlist and an SDF."
During that same post-DAC'99 time frame, Ross Smith of Theseus Logic also wrote. "Ultima's ClockWise is a tool that modifies clock skew to improve margins by changing branching points and inserting buffers, about 20 percent more than normal," Ross said in his e-mail. "It is a point tool used after placement and before routing. As a side effect, it also reduces peak current by 30 to 40 percent."
Then, six months later in ESNUG 338, Jon Stahl of Avici sent in a review about Chip Architect. It that review, Jon made the side comment: "We're looking at integrating Ultima's ClockWise tool here because they have a useful skew solution. The Chip Architect people are doing a zero skew tool; ClockWise can skew your design to get additional set-up time."
And last month, Bob Wiegand of Ensoniq jumped in. "At the SNUG'00 vendor fair, I saw a tool from Ultima called ClockWise," wrote Bob. "Caught my attention since Chip Architect and PhysOpt don't have this capability yet (but will soon). However, ClockWise claims to be able to use clock skew as an advantage, moving the clock edges to fix setup/hold times. Their idea both intrigues and scares the hell out of me. This would have very serious implications on hold violations on scan flops."
Last week in ESNUG 350, Willis Hendley of Sun Microsystems replied to Bob's concerns. "As silicon scales down farther below 0.18 micron, we have to use localized skew. This is because global clock skews with useful cycle times and hold specifications won't be possible," wrote Willis. "Luckily, scan flops can have increased delay on their scan-data-in ports to handle mismatches between 'useful skew' on the functional path and 'nonuseful skew' with respect to the scan inputs. The logic cone depth and wire delays driving scan-data-in is typically much shallower than regular data inputs."
Just yesterday, after some snooping, I discovered that LSI Logic, Matrox, HP, Texas Instruments and Philips were all doing evals of ClockWise. I wonder if there are any ClockWise tape-outs yet ( www.UltimaTech.com).
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a contract ASIC Designer, and loves hearing from engineers at jcooley@world.std.com or (508) 429-4357.
