Sometimes, when I'm caught up in a project, I get a little bit behind in my e-mails. In August I ranted at Cadence for not selling 100 percent of its ownership in its Tality IPO. It's now November, and I've just now found the time to read the e-mail responses to that column. And Tality got very interesting when people started telling me to check out that Tality S-1 filing with the SEC.
It turns out that the "design factory" idea has been massively unprofitable for Cadence For the past five years (from fiscal 1995 to 1999), Cadence forked out $785.4 million and only earned back a meager $460.6 million, according to the Tality S-1 filing. For every dollar Cadence put into the "design factory," it lost 41 cents. And for the first six months of FY 2000, it lost an additional $27 million on $90 million of revenue. That means each Tality engineer pulls in about $180,000 per year but would need to pull in at least $234,000 for Tality to break even. No wonder Tality hasn't IPO-ed. It never will. It's fiscally unsound.
To make matters worse, three years ago Cadence paid Synopsys $11 million for Design Compiler licenses for its then-1,300 consulting engineers. Now, on the last day of October of this year, Cadence bought what I estimate to be $25 million worth of Synopsys Design Compiler, PrimeTime, ATPG, TimeMill and PathMill licenses for its 1,000 remaining Tality engineers.
Does Cadence corporate marketing know what kind of message this sends to Cadence customers? "We may sell Ambit-RTL, Ambit-DFT, Pearl, and many flavors of transistor tools at Cadence, but when 'We' make chips, 'We' use Synopsys tools! Do as we say, not as we do, OK customers?"
In contrast, the 350 consulting engineers at Synopsys pull in about $120 million in revenue. At $343,000 per-engineer revenue, they're a money-maker for Synopsys. Only about 140 Synopsys consulting engineers do Tality-style turnkey chip design, with the remainder doing methodology consulting. And almost all these engineers use an all-Synopsys tool flow (the exception: eight Cadence/Avanti P&R licenses because Synopsys has no such back-end tools yet.) "When we make chips, we actually use our own tools here at Synopsys" is their message.
Mentor Graphics' 150 consulting engineers each pull in about $330,000, and they don't even do turnkey chips. "We decided five years ago turnkey designs were in direct conflict with our customers," says Wally Rhines, chief executive officer of Mentor. "So we focus on teaching customers to fish, instead of selling them fish."
When I first saw the Forrest Gump movie, I didn't fully understand that "stupid is as stupid does" quote. Now that I've looked deeper into the Cadence Tality IPO, I see how it may apply in the EDA world.
John Cooley runs the E-mail Synopsys Users Group (ESNUG), is a Contract ASIC Designer, and loves hearing from engineers at jcooley@world.std.com or (508) 429-4357.
