I recently played host to some family members from the East Coast. A Napa Valley wine trip was on their agenda as a necessary part of doing California. It was great to see everyone, how they've changed and yet are still the same.

So, here I am. They've flown home and I have the empty wine bottles over by the kitchen door, ready to go out with the recycling next week.

This image got me reminiscing. In 1987 at Ardent Computer, we were one of the first to embrace Verilog-XL, the logic simulator from Gateway Design Automation, for the specification and simulation of ASICs.

Back then, we had fewer than a half-dozen Verilog-XL licenses, and they were a hot commodity. In truth, the machine that was up to the task of running the simulation was the hot commodity. Perhaps it has faded from my memory, but I seem to recall a 5-Mips box with 64 Mbytes of memory cost $150,000.

We had a problem: how to allocate simulation time on these machines. One could use the "early bird" approach-check a machine and if it doesn't appear to be running anything, start up your job. This broke down because two designers would check, determine that a machine was free and then initiate a job. In those days, Unix was only about as robust as Windows 95 is today, and two large jobs starting at the same time would often lock up the machine. Even if the machine didn't crash, we were wasting resources-the two simulation runs would each get less than half the compute power of the machine. Hence, we were wasting one of our precious assets: a Verilog-XL license.

To indicate the temporary "ownership" of one of these machines and the associated Verilog-XL license, we resorted to the use of a token to represent the machine.

My office mate at Ardent was an oenophile and, as he lived up in the Santa Cruz mountains, once a month he would receive at work a UPS package from Ridge Winery containing a few bottles of choice red and white varieties. Since we needed tokens for each machine and since we had these empty wine bottles he brought back into work to recycle, the solution was obvious. The Chardonnay came to represent the machine known as Narak. The Zinfandel was Rhea. And so on.

If you wanted to run a simulation on a particular machine, you walked the circuit by each office or cube of the likely designer who might have the wine bottle representing that machine. Once found, you asked that person if you could use that machine next. If yes, you picked up the bottle by the neck and it was yours until you chose to yield it to someone else.

It's no surprise that Peter Eichenber, the wine fancier, John Sanguinetti, our manager, and I recognized an opportunity when Cadence, buyer of Gateway Design Automation in 1990, placed the Verilog hardware-description language in the public domain. We seized the chance to address the bottleneck by producing Chronologic Simulation's VCS, the first Verilog compiler.

Like the wine bottles at Ardent, bottlenecks in design automation shift. Creating a comprehensive test suite is the latest one. The recent introduction of coverage tools is an attempt at addressing the problem by diagnosing what parts of the design haven't been tested.

Of course, this is just the beginning. What's needed is a surefire way to build a comprehensive test suite for your design and end the bottleneck.

— Michael (Mac) T.Y. Mcnamara is president and cofounder of Surefire Verification (Campbell, Calif.).