"Silicon is free" is widely accepted as a driver for system-on-a-chip design. In a large IC, as long as the necessary intellectual property can be assembled and the methodology can route to meet timing constraints, then the variable cost of extra features is zero.

But there are second-order effects, and they change with geometry and gate count. If they bump up against basic physical limits, they can swiftly become first-order effects. At that point, either the notion that silicon is free or the design methodology-or both-breaks down.

One such effect is power dissipation. The physical issue here is the chip's operating temperature limit, a constant for all silicon ICs. Given the trend for power in large chips to increase over time, we can expect to hit a wall eventually. So where's the wall?

Not surprisingly, it's in system-on-chip design, initially in areas where high unit volumes and low cost are important, such as graphics, multimedia and consumer equipment.

VLSI power depends on technology and design, but a reasonable rule of thumb is that power in a given architecture increases by 30 to 35 percent per year. At that rate, it doubles every two years.

Consider the dynamics of managing power. The most quantifiable is the complexity and cost of IC packaging and cooling. There's a distinct shift around 2 W. Below that, inexpensive plastic packaging is normally adequate; beyond it, power quickly becomes a concern.

At about 3 W, significantly more elaborate packaging (ceramic, for example) becomes necessary, at an incremental expense of several dollars per chip. At 4 to 5 W, heat sinking is a requirement. Hit 6 W or so, and airflow is needed. And by 8 to 9 W, cooling engineering is a serious, sophisticated affair.

A wave of consumer ICs in the 350,000-gate, 1.5-to-2.5-W range is entering production. Suppose you've got one of those designs-a large one. In two years, it will be at 5 W, and two years after that, 10 W. So over three or four years, the same design will run the gamut from basically no power concerns to the major leagues of thermal engineering. For many applications, that won't be acceptable, and it will put a cap on functionality and performance. Extra silicon is still free-you just can't use it.

Scary, isn't it? But then no one expected fans in laptop computers, either.

Today's design methodologies, largely evolved around moderate-complexity ASICs, don't help. Most VLSI design teams handle power issues the way they once handled timing issues: loose estimates early in design, followed by detailed verification just before tapeout (or even multiple tapeouts on the same chip). In system-on-a-chip ICs, the approach works as long as you don't actually have a problem. Since most of the power in a complex IC is determined in the chip's architecture, by the time the team finds the problem, it's too late to do much about it-except add fans and heat pipes.

The answer lies at the beginning of development, not the end. What's needed is a design methodology that incorporates power management from the chip concept onward: up-front budgets, early trade-off analysis and successively more refined estimation from start to finish.

It's a shift of focus that few design groups have made. But it's one of the costs of free silicon.

— Eric Filseth is vice president of marketing for Sente Inc. (Acton, Mass.).