Physical chip design became a real challenge once the 1-micron barrier was crossed. At 0.8 micron, the talk was that "all the tools are broken." At 0.5 micron, we had a "deep-submicron challenge." Now, with 0.25-micron silicon, achieving timing convergence between physical and logical design has become such an issue that EDA vendors, silicon vendors and end users alike are scrambling to patch together solutions that will at least allow them to get current designs into manufacturing.

Ten years ago, the focus was on managing gate delay. Interconnect delay contributed such a small amount to the overall chip delay that it was either ignored or assumed to be negligible. Similarly, signal-integrity and quality issues such as crosstalk and electromigration were rarely a concern.

At 0.25 micron and below, both chip performance and signal integrity are dictated by the interconnect topology. Even with copper interconnect and low-k dielectrics, interconnect contributes in excess of 45 percent of the total delay at 0.18 micron and below. And because the wires are taller, thinner and closer together, coupling capacitance (key to crosstalk) is the dominant form of capacitance designers must worry about. No existing physical-design tools automatically address this issue.

Synthesis is usually the final step performed in front-end logic design. The output of synthesis is a gate-level net-list containing cells from the silicon vendor's library chosen to meet the designer's functional and performance constraints. Cell selection and sizing are determined by using statistical wire-load models to "estimate" the actual interconnect loading that will exist in the physical layout. Those wire-load models are essentially random numbers that do not correlate well with the real delays due to interconnect and coupling capacitance. The actual interconnect load and resulting performance in the physical layout usually differ significantly from what synthesis predicts.

To solve that problem, some vendors are pushing RTL floor planning. The basic premise is that predictions can be made up front that will give better performance information than possible by doing full synthesis. But if synthesis can't give good timing predictions, how can anything based on even rougher estimations of the design do better? At best, designers using RTL floor-planning tools can expect a 5 to 10 percent improvement over the use of statistical wire-load models without floor planning.

Some are attacking the problem via brute-force parallel computing. It is accepted that there will still be iterations, but that the use of parallel computing power will slash the time required for each. Simulation experts have tried, but failed, to employ the same technique for speeding up large simulations. Throwing more hardware at this problem is not likely to fix it.

Meanwhile, designers iterate, iterate and iterate some more to try to get timing convergence. They buy new tools to make up for the inadequacies of the old ones.

The physical design space is an open market waiting for new approaches to free users from today's Band-Aid solutions. New ideas are likely to come from the startups, not the large companies that have to protect the tools and methodologies they already have.

— Rajeev Madhaven is president of Magma Design Automation (Palo Alto, Calif.).